Re: Open source processors

On Jun 8, 3:19 am, Tommy Thorn <tommy.th...@xxxxxxxxx> wrote:
I wrote:
In fact, all the options for getting that
extra write port pretty much annul the performance benefits of running
multiple instructions. (And I haven't even started talking about the
bypass network and the hazard detection here).

rickman kibitzed:

You can use two write ports on block rams.  They can be hard to infer,
but they can always be instantiated.

Your register files are write-only? You can't have two write ports to
a memory block if you need to read arbitrary locations as well.

Unfortunately there isn't any one good solution, tough there are some
options. For example :
- Time multiplexing (there goes the benefit of superscalar),
- Banking (Complicated and performance depends on few conflicts),
- Inferred from logic (expensive, but sometimes the best option), and
- "Distributed": represent each location as the sum of parts (one
cycle extra write latency and uses a lot of memory blocks, eg. 2w4r =
10 blocks).

Tommy

I think you are mistaken. The read and write must share an address,
but you can do either a read or a write on either clock cycle on each
port. If you need dual ported ram that can do both read and write
simultaneously, you can run the RAM at *double speed* and in effect
multiplex it. I doubt that the block ram in FPGAs will be the speed
limiting factor even when running at a double speed clock.

Rick
.

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