Quartus II negative bus dimensions in Schematic file

This question is Quartus II specific but I figured since this would
the proper place to find at least one person with this problem.

I want to use the fixed point package provided here:
http://www.accellera.org/apps/group_public/documents.php?wg_abbrev=vhdl

I can compile the library and use the files, but a problem arises when
I create a schematic file and try to synthesize. To use the fixed
point numbers I have to declare the bus width like so: var_name sfixed
(1 downto -30)

When I create a block out the file and try to synthesize it, I get an
error about illegal bus width "-30". Is there a way to get around
this? Or I cannot use negative numbers as a bus width?

Thanks
.

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