Re: Two stage synchroniser,how does it work?

On Apr 8, 2:48 pm, "kadhiem_ayob" <kadhiem_a...@xxxxxxxxxxx> wrote:
Thanks Muzaffar,

I am not trying to achieve any practical problems. Thank goodness I have
designed complete multiclock modulator systems for decades now.
I am simply looking inside "my thoughts" and make sure I am not getting
too old.
I possibly understand data is either 0 or 1, the absolute value doesn't
matter but the sequence does matter ofcourse and that a few clk latency is
not an issue but the sequence of 0 and 1 from one clk must pass to second
clk domain. Well it does in practice.
The crux of my disorder lies in our thinking model: flip1 is at the mercy
of its input and is thrown into chaos from time time. flip2 absorbs the
impact, fair. Are we saying data sequence at Q1 correctly follows D1
eventually despite the chaos? in that case no problem but literature says
Q1 can be '0' or '1' or in between or oscilating or so then settle as '0'
or '1'...
if it does settle at D1 value then please ignore this post completely.
It is simple primary math of vectors(ignoring latency):
D1 => Q1
Q1 is D2
D2 => Q2

so if Q2 = D1 then Q1 = D1
Hence Q1 settles finally at end of clk period to D1(current or previous or
next)

I think you have it correct. This is an unusual way of thinking about
it however. But yes, Q1 has to settle by the time of the next active
clock edge or Q2 will also be metastable. The point is that there is
*no* time interval that guarantees that Q1 will be stable when the
setup and hold time is violated. But the probability of metastability
becomes very, very, very small when using current technology and with
time periods of just a few nanoseconds (like 5 to 10). The purpose of
FF2 is to assure that the circuitry it is driving does not see the
output of Q1 which will not meet the delay time spec of the FF. With
FF2 in the path, the 0->1 or 1->0 transition is delayed another clock
cycle, but will transition monotonically and will meet the output
delay timing spec, even when Q1 does not.

Rick
.

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