Re: Two stage synchroniser,how does it work?

Thanks Muzaffar,

I am not trying to achieve any practical problems. Thank goodness I have
designed complete multiclock modulator systems for decades now.
I am simply looking inside "my thoughts" and make sure I am not getting
too old.
I possibly understand data is either 0 or 1, the absolute value doesn't
matter but the sequence does matter ofcourse and that a few clk latency is
not an issue but the sequence of 0 and 1 from one clk must pass to second
clk domain. Well it does in practice.
The crux of my disorder lies in our thinking model: flip1 is at the mercy
of its input and is thrown into chaos from time time. flip2 absorbs the
impact, fair. Are we saying data sequence at Q1 correctly follows D1
eventually despite the chaos? in that case no problem but literature says
Q1 can be '0' or '1' or in between or oscilating or so then settle as '0'
or '1'...
if it does settle at D1 value then please ignore this post completely.
It is simple primary math of vectors(ignoring latency):
D1 => Q1
Q1 is D2
D2 => Q2

so if Q2 = D1 then Q1 = D1
Hence Q1 settles finally at end of clk period to D1(current or previous or
next)







.

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