Re: Two stage synchroniser,how does it work?



No. A "metastable" Q output from the first stage does not refer to a
"wrong" output value, such as it being a "1" when it should be a "0",
but
about the Q output getting stuck half-way or oscillating for a while,
which can happen if its D input was in transition when it was clocked.
If
that metastable Q output was fed to, for example, an incremental
counter,
then that counter could do something worse than incrementing or not
incrementing -- like making a big jump to a completely different value
because its own setup time was violated. *That* is why metastable
states
are considered so nasty.

Adding a second d-type with a short propagation delay from the first
means that there's a whole clock cycle for the first stage to come out
of
metastability and give a good setup time for the second D-type, so that
*its* Q output is either a secure 0 or 1 but not something between the
two. Thus it becomes a negligible source of error compared to a
system's
overall reliability. Understand now?

unfortunatley it is not convincing. it is ok for a discussion of
Metsatability per se but not data transfer.

the above argument states clearly that first Q output is not copy of D
input but is unstable halfway. So is the input to second flop. Now lets
look at value rather than stability at second Q output, stable yes but
correct who knows...

Sorry for being so microanatomical but history has other examples when
consensus doesn't fit reality

kadhiem


.



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