Re: clock multipliers, dividers, and more clocks...

On Apr 5, 8:38 pm, Mark McDougall <ma...@xxxxxxxxx> wrote:
rickman wrote:
Are you sure about that? I haven't looked at this detail on a Xilinx
part in a while, but the Lattice parts allow a clock source to be from
the general routing. Because of the long delay in the routing, this
won't be usable to clock input data that is relative to that clock,
but it can be used internally.

Altera Cyclone devices have a limited number of pins connected to the
global clock network. Admittedly, I'm not sure about Xilinx devices.

But that wasn't the question. The point is that regardless of how
many pins are directly connected to the clock routing, there is often
a way to connect from the general routing to the clock routing. That
means that you can connect *any* signal to the clock routing, not just
external signals on the clock pins. This includes signals from other
I/O pins as well as signals from any logic inside the device.

I can't imagine that a vendor would limit the clock routing to
external signals from a handful of pins. I guess they do that in some
CPLDs, but I have not seen it in FPGAs.

The clock pins are for a *direct* path from the I/O pin to the clock
routing with a *minimum* of delay. This allows minimum and
predictable setup times without using a DLL or the like.

Rick
.

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