Re: How big is my vhdl and am I approaching some size limitation on the chip.

On Mar 21, 10:14 am, John Adair <g...@xxxxxxxxxxxxxxxx> wrote:
CPLDs are generally very small devices compared to a FPGAs. They are
generally slightly easier to use for the novice but I won't let that
put you off going for FPGA. Virtex-IIPro is a very old and expensive
familiy now. Xilinx offers 2 sets of families. The Virtex range is
big, very fast and expensive. Virtex-5 is readily available with
Virtex-6 just announced. The Spartan families go from small to medium
size in comparision. Coolrunner etc. I would describe as tiny to give
a reference.

If you have the ability to choose a part now then the Spartan-3A or
Spartan-3AN are probably a good choice. The S3-A needs an external
Flash memory that is used to configure the device at power up. The S3-
AN has an internal Flash that is used for that purpose.

The smallest S3-AN is the XC3S50AN and it has about 1400 flip-flops as
a comparision to the Coolrunner with 512 macrocells which have 512
flip-flops available. It is very difficult to make a simple
comparision between CPLD and FPGA technologies but I would suggest
just trail building the design in a XC3S50AN to get a better
comparision. ISE Webpack I presume you already have and it will only
take a few minutes to change the part type and re-build.

If you do want a development board we supply lots of choice with some
more shortly in this market sector soon. You may find some of the
links on our Techitips page useful -http://www.enterpoint.co.uk/techitips/techitips.html.

John Adair
Enterpoint Ltd.

On 21 Mar, 05:14, jleslie48 <j...@xxxxxxxxxxxxxxxxxx> wrote:

On Mar 21, 12:12 am, rickman <gnu...@xxxxxxxxx> wrote:

On Mar 20, 3:15 pm, jleslie48 <j...@xxxxxxxxxxxxxxxxxx> wrote:

On Mar 20, 2:58 pm, jleslie48 <j...@xxxxxxxxxxxxxxxxxx> wrote:

On Mar 20, 1:41 pm, Mike Treseler <mtrese...@xxxxxxxxx> wrote:

jleslie48 wrote:
and when I added some digital outputs, the %'s went up, but then I
added a whole bunch of logic, and nothing changed,

If the number of cells or Pterms used didn't change at all,
I would expect that a "whole bunch" of logic does not make it
out to a pin. I would run a sim to check.

-- Mike Treseler

ahhh, well that is a bummer. I just tied the output to a pin and now
I"m getting:

Fitting...
.
ERROR:Cpld:1063 - Design requires at least 947 macrocells, exceeds
device limit
512.
ERROR:Cpld:1062 - Design contains 2004 unique product terms, exceeds
device
limit 1536.
ERROR:Cpld:1064 - Design rules checking error. Fitting process
stopped.
...o
ERROR:Cpld:868 - Cannot fit the design into any of the specified
devices with
the selected implementation options.

any idea on how to make it fit?

ok, before I added my functionality, I had:
Macrocells Used Pterms Used Registers Used Pins Used Function
Block Inputs Used
379/512 (75%) 831/1536 (55%) 354/512 (70%) 118/176 (68%)
779/1280 (61%)

so from my errors, I can see I added some 600 macrocells, and 1200
pterms,

how can I find out who is the piggy, and what can I due to trim things
down?

I don't think you really got an answer to this question. To some
extent you can look at the code and estimate the number of macrocells
or other logic elements used. But to measure it, you need to break
the code into modules and let the tool tell you about each module
separately. In an FPGA the logic has a finer grain, so there are not
as much optimizations to affect these counts when you use the block
all together. But a CPLD can put a lot of logic into each macrocell
and will be much more limited by the FF count. Your design counts
above indicate that your design uses 1300 FFs and your CPLD only has
512 FFs. Not a good fit!

You won't find much in the way of optimizations that will make this
fit. The best thing to trim your logic is to change your algorithm.
If there are parts of your design that can run slowly compared to the
clock rate, you can let them run sequentially rather than in
parallel. But if your design has to run at the full rate of the clock
with everything in parallel, you just need a larger part. So take a
good, hard at your design and see if there is anything you can do to
reduce it.

also, what is a macrocell and pterm?

I think these got answered, but a little more detail... A macrocell
is the unit block of a CPLD. It typically include one or two FFs, an
output, often to a pin along with some amount of logic. The logic in
a macrocell is made of p-terms and OR gates. P-terms are very wide
AND gates with inputs from all of the inputs to that block, all of the
FFs in that block as well as, in some devices, some inputs from other
macrocell p-terms. The p-terms of a given macrocell are OR'd together
to produce the input to the FF or it can be routed directly to the
output. There is also a p-term or two devoted to controlling the tri-
state driver on the output. The OR gate and FF outputs are connected
back to the logic matrix for use in other or the same macrocells.
Some devices have "buried" FFs which allow some of the logic in the
macrocell to be split off and used with this second FF, but the output
can only be routed back to the routing matrix, not an output pin.

That is a lot to absorb from a description. I am sure the data ***
has a picture that is very clear and can portray the detail better.
The main thing to understand is that the p-term (and) are unlimited
(or more accurately only limited by the inputs to the block routing)
and an FPGA typically has much smaller LUTs, usually 1 LUT per FF or
sometimes 4 LUTs to 3 FFs. So a CPLD is often FF count limited while
an FPGA is mostly LUT count limited. Certainly there are things you
can change in your design to use more logic and fewer FF to target
CPLDs. But I think it will be a major job to cut the design size by
more than half!

I originally ran this program on a virtexII, and everthing looked
liked it
was pretty small and effecient:

Device Utilization Summary
[-]
Logic Utilization
Used
Available
Utilization
Note(s)
Number of Slice Flip Flops
1,282
27,392
4%

Number of 4 input LUTs
1,545
27,392
5%

Logic Distribution

Number of occupied Slices
1,302
13,696
9%

Number of Slices containing only related logic
1,302
1,302
100%

Number of Slices containing unrelated logic
0
1,302
0%

Total Number of 4 input LUTs
1,589
27,392
5%

Number used as logic
1,545

Number used as a route-thru
44

Number of bonded IOBs
Number of bonded
15
556
2%

IOB Flip Flops
1

Number of RAMB16s
2
136
1%

Number of BUFGMUXs
3
16
18%

but I cant seem to compare these two chips, the VIRTEX II vs the
XCR3512XL-12-PQ208
its apples to oranges, how does it work?

The 3512 has 512 FFs in the macrocells. (I think they also have input
FFs) The FPGA is using some 1300 out of 27,000! The FPGA is using
1500 LUTs for logic. It does not look to me like that couldn't fit in
the logic of 512 macrocells. But the number of FFs has to be
reduced. Are they all necessary?

Rick

"But I think it will be a major job to cut the design size by more
than half!"

Well this is what has me scratching my head, I only added one uart to
the 3512, the listing from the Virtex II has two
separate UARTS, to make up the 1300 slice flip flops. I've only
moved one of the uarts to the 3512 so far and it blew its top. I
can't see how one uart can take up the entire chip, Or that the
difference between the $90 3512 and the
$1200 Virtex II Pro?

I'm not sure of what you are getting out with me reducing the number
of FF's, I'm just getting the hand of VHDL but I'm not aware of what
code makes up the FF's, I inlcuded the code I put in up above, It
seems very straight-forward, state machine,

"The FPGA is using some 1300 out of 27,000! " I'm assuming you mean
the 1282/27,392 number. What I'm guessing is that in order for this
design I have to get these 1282 to fit into the the 512 macrocells of
the 3512 but I can only put 1 in each macrocell, aka I've got to get
down to under 512 slice FF. Thats not counting the problem I'm having
with the pterms,- Hide quoted text -

- Show quoted text -

John,

You have me very interested in this board and your products. I
imagine I will be getting one to try out very soon. I am concerned
though, you have put on the raggedstone1 board voltage regulators
right in the middle of the GPIO pin
layouts. In the case of he RHS DIL headers, there is a voltage
regulator (read: huge heat source that needs to be ventilated) between
the mid and right column. You have a similar arrangement on the LHS
as well. I will need to put a daughter board onto this card and I
would love to snap it in right on top of the DIL headers, but I'll
have to trap that voltage regulator on 4 sides, Its even worse since
you put the ground on one column and power on the other so I can't
even just have the daughter card on the two headers and skip the third
letting the voltage regulator vent.


.

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