Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz

On Mar 14, 8:49 pm, rickman <gnu...@xxxxxxxxx> wrote:
On Mar 14, 11:11 am, Herbert Kleebauer <k...@xxxxxxxxx> wrote:

rickman wrote:
http://www.bitlib.de/pub/mproz/mproz3_e.pdf(withnternal RAM)
http://www.bitlib.de/pub/mproz/mproz2a.pdf ;(with external RAM)
Are you saying that this processor can't be made smaller?

As long as I don't see it, I don't believe it.

Ok, I guess that pretty much limits the discussion.

Registers
can be stored in memory rather than FFs.  

There are no registers at all (beside the 15 bit program counter and
the 2 bit status register). It is a two (mproz2) or three (mproz3)
address machine with only memory operands.

Yes, I read the description and I did not figure it out completely.
This is a bizarre machine that has no practical value that I can see.
You are defining it as a "minimal" machine because of its FF count.
But it is just trading off FF based registers and LUT logic for memory
usage.  I don't see how that is "minimal" in any real way.  Three
words of memory to perform an ADD???  That's not minimal.

By processing the registers
serially the logic can be greatly reduced at the expense of more
control logic.

You have two operands and one result but there is only one data
path to the serial memory. This means, you at least need one
registers to temporary hold one of the operands and an address
register to hold the address of the second operand. Mproz
also only needs two temporary registers. But the control logic
for a serial design becomes much more complex. Mproz only has
8 states, so the state machine can be implemented with only three
flip-flop's (actual it's done as a one-hot machine with 8
flip-flop's because this reduces the logic count).

Why do you need temporary registers?  If the memory is serial, each
bit can be fetched as needed.  You are imposing a word access method
on this.

BTW, I don't know why you are stating the FF count as if this were a
good measure of design size.  Most designs in FPGAs use more LUTs than
FFs.  The logic of this beast is likely  With 65 FFs this may well be
designed for a CPLD which has more capable logic with each FF.  But

As far as I remember, mproz uses about 250 two-input gates, that
should fit well with 65 flip-flop's.

How about the memory?  I expect that will be an order of magnitude
larger than the machine itself, even for a small program.

Rick

right

mproz stands for minimal.. so it is minimal in terms of instructions
and resources
in the tradeoff of speed (8 clocks!) and program size

the machine is funny, it can do subroutine calls by patching own code
on the fly
that is self modifying code is needed, normal instructions are 6 bytes
or 8 bytes
if new immediate constant is needed. Also shift and rotate are very
clumsy i guess

so the maximum 32K memory space would only hold say about 5K
instructions !

Antti









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