Re: UART RS232 "hello world" really taking shape now.

On Fri, 13 Feb 2009 12:24:36 -0800 (PST), jleslie48 wrote:

expanded to this now:

op_GOTOL & 02 & -- ok here is the new gotol, it will
-- jump to the label rather
-- than the array index, so the length
-- of the strings no longer
-- needs to be calculated

Well done for making this work - I reckon it's a good
"rite of passage" and you should be able to make progress
with reasonable confidence now.

However, I question the motivation. Wouldn't it have
been way, way easier to write a little "compiler" to do
all the necessary string length and address calculations
in advance, generating a piece of VHDL code (or a Xilinx
memory-format file) to graft into your project, so that
you could stick with the nice simple "goto address"
hardware? Scanning the program to find its labels
must be a non-trivial overhead.

all is working, now, and I'm quite happy with this layout. I imagine
after every op_MESSAGE I will be placing a
op_WAIT_FOR_LABEL in the future. My UART mesages will all reside in
this packet, with the Top process changing a LABEL_TO_BE SENT byte and
zeroing it out on completion. In this way My entire array of canned
output messages can be called up on demand.

Consider a redirection table, where the addresses of
the various strings are stored in a simple lookup table
indexed by label number.

then onto dynamic messaging (aka, type 5 values
into the RS232, and send the message, "the values are,
x1, x2, x3, x4, >x5 and the sum is yyy").

I still don't understand the ideological barrier to using
a soft-core CPU in the FPGA. However cunning your
programmable functionality, you'll soon enough encounter
a problem where it's not cunning enough, but real SOFTWARE
would easily do what you need. The CPU doesn't need to be
big or clever - but it *does* need to be a real computing
engine, which is unlikely to be true of your string-indexing
machine....
Picoblaze is FREE, by almost any reasonable measure. Having
such a soft-core on your FPGA doesn't call your manhood into
question, nor does it inhibit your ability to do very fast
stuff (far too fast for a CPU) elsewhere on the FPGA.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@xxxxxxxxxxxxx
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
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