Re: Is this phase accumulator trick well-known???

Jonathan Bromley wrote:

hi comp.arch.fpga,
(accidentally posted to comp.lang.vhdl a few moments ago- sorry)

The question - repeated after the explanation - is: here's what I think is a nifty trick; has
anyone seen it, or been aware of it, before?
I can't believe it's really new.

As far as I know, the usual system is to use a power of
two modulus and supply enough bits to get the required
accuracy. It is then easy to take the top bit as
a (close enough to) 50% duty cycle clock.

I have been messing around with baud rate generators
and suchlike - creating a pulse that's active for
one clock period at some required repetition rate -
and wanted to try a phase accumulator technique instead of a simple divider. That makes it far easier to specify the frequency - it's simply the
phase-delta input value - and easily allows for
non-integral divide ratios, at the cost of one
master clock period of jitter.

The phase-accumulator produces pulses with a
repetition rate of Fc * M / N where Fc is the master clock, M is the phase delta
and N is the counter's modulus. However, to get
the huge convenience of specifying M as the required
frequency, I must make N be equal to the frequency
of Fc, and this is unlikely to be an exact power of 2.
So the phase accumulator works like this:

on every clock pulse...
if (acc < 0) then
add := acc + N;
output_pulse <= '1';
else
output_pulse <= '0';
end if;
acc := acc - M; -- unconditionally

This is fine, but it means that on the "wrap-around"
clock cycle I must add either N-M to the accumulator;
if either M or N are variable, that costs me another
adder.

Adders are pretty cheap in FPGAs. It would take some
work to see if your method is a net savings.

Today I came up with an intriguing (to me) alternative:
on the wrap-around cycle, add N to the accumulator;
on the immediately subsequent cycle, add (-2M); on
all other cycles, add (-M). This is of course rather
easy to do since 2M is just a left shift. A few trial synthesis runs convinced me that it will give
measurably better performance than the two-adder
version. VHDL code is appended for anyone who wants
to play.

It seems to me that needs an additional MUX to
save an adder. In 4LUT logic, I believe that
is pretty close to the same in CLBs.

My question is: has this trick been published anywhere?
Or is it something that "those skilled in the art"
already know about? I haven't seen it before, but that simply means I probably haven't looked hard enough.

There are a large number of tricks that have been used
over the years to make computer arithmetic faster. Many of
those tricks aren't as effective in FPGA logic, so new
ones will have to be developed.

-- glen

.

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