Re: UART RS232 "hello world" program trial and terror.

On Jan 29, 8:27 pm, glen herrmannsfeldt <g...@xxxxxxxxxxxxxxxx> wrote:
rickman <gnu...@xxxxxxxxx> wrote:

(snip)

I believe the same is true for VHDL. But the code above is not using
an operator. It is using a conditional assignment based on an IF.
o2_int <= '1';
if o1_int = '1' then
o2_int <= '0';
end if;
The IF evaluates the signal literally. If it is a '1', then o2_int
gets '0'. If it is ***any*** other value o2_int retains '1'.

I believe verilog is slightly less literal, but in this case
with the same result. For verilog, if o1_int was 1`bz then
o1_int=1 would be 1`bx. For if(), 1`b1 is true, everything else
is false. Verilog has the === and !== operators for literal
comparisons including 1`bx and 1`bz.

I might have written

assign o2_int = ~o1_int;

or

assign o2_int = !o1_int;

both of which will assign 1`bx if o1_int is 1`bz.

I would not use tristate logic, partly because of the problem Andreas
points out, but mainly because it can be confusing and misleading. I
think it is much better to change the code to match the current
devices than to retain the code in an obsolete form. I don't think
there are any issues of "but this code works"! If you are porting it
to a new device and most likely new tools, it has to be verified from
scratch anyway. So fixing the out of date code would not add
significantly to the cost.

There are some people interested in porting old computer
designs, such as the Apple II, to FPGA. In that case, it
might make sense to include the original tristate lines.

Any design with real (74LS367 for example) tristate buffers
should work, but it might be that some such designs depend
on the bus staying in the previous state for some fraction
of a second after all buffers are disabled. That would
seem to me a design bug, but one that might still exist.

I don't know what the synthesis tools do if you put a
keeper on the tristate bus.

This is a good example of what I was thinking of. If I were porting
such a design, although "port" is not really the correct term because
there is no existing HDL code, I would not describe tri-state buffers
in my code. I would describe a selection function which was a top
level OR with each of the "tri-state" buffers being replaced by an AND
gate. If there were timing issues that required the bus to "remember"
the last driven state, I would add a latch with the enable driven by
an OR of all of the individual enables. I don't see how you could
expect a synthesis tool to do anything other than to replace the tri-
state drivers with the OR-AND multiplexer and I don't see any reason
to even try to duplicate a design at that level.

Rick
.

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