Re: FPGA partial/catastrophic failure mode question
- From: Neil Steiner <neil.steiner@xxxxxxxxxxxx>
- Date: Fri, 19 Dec 2008 16:58:57 -0500
I once went to a talk by someone running Linux on a PPC in a Xilinx
chip, and then doing partial reconfiguration from that running
Linux system. You do have to be careful not to configure yourself
out, though. Also, no protection against failure modes including
the PPC and its connection to the configuration lines.
Thank you for stating my mantra! ;)
The key to doing this successfully is to give the system a dynamic model of itself that stays in sync with the changes that it undergoes. That not only tells it what wires and logic are or are not in use, but also allows it to avoid clobbering existing wires or logic or injected defects.
With that foundation in place, I have demonstrated the ability to implement or remove EDIF circuits at will, and arbitrarily add, extend, trim, or remove connections between those circuits and/or the base system, without requiring the slot model mandated by the PR flow. It turns out that partial active reconfiguration works really well if one is careful to avoid the kinds of things you allude to.
But returning to the original point of the post, if FPGA failures are typically sudden and catastrophic, then my ability to avoid masked defects is not particularly useful.
.
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