Re: Sampling a clock

Instead of complicated state machine to detect glitches or runt pulse,
one can simply use the clock signal to toggle a T-flipflop. If you
observer a pulse of shorter duration than expected then there is a
glitch or a runt pulse.

Use the 6Kz clock and divide it by 2 using a flipflop. Put no other
loads on this clock like other than single flipflop.
Bring out the divided clock to the output pin and observe on the
scope.
Set the trigger to trigger on any pulse less than time period of the
3KHz expected signal.
If you get a pulse of shorter time period then you have a glitch or
runt pulse.

If the device has DDR registers than they would be ideal and you can
get 6kHz output instead of 3 KHz.

Brijesh





On Dec 10, 1:05 pm, Rob <robns...@xxxxxxxxxxxxxxx> wrote:
On Dec 10, 12:14 pm, KJ <kkjenni...@xxxxxxxxxxxxx> wrote:



On Dec 10, 11:43 am, Rob <robns...@xxxxxxxxxxxxxxx> wrote:

There are no asynchronous inputs.  All the inputs are sync'd to the
incoming slow 6kHz clock.  The other fast internal FPGA MHz clock is
for something completely unrelated and has nothing to do with the SM.

Rob- Hide quoted text -

Maybe add a free running counter that is clocked by the 6kHz clock
that counts from 0 to 24 and then goes back to 0 resetting it only
during powerup.  Bring the counter out to debug pins.  If your
original hypothesis is correct that "...there is a spurious edge which
my SM reacts to, thus causing erroneous data to be latched." then this
counter would at some point end up at a non-zero count between
transmissions (I'm assuming here that the transmissions are not
continuous and there are identifiable gaps in time during which the
state machine is waiting for the next 25 clock transmission to
occur).  With that setup you can also look for times when the counter
changes states quicker than the expected 6 kHz rate.  It can be a tad
difficult depending on what equipment you can bring to bear and how
many debug pins you have in your FPGA, but at least it gives you a
direct view of flops inside the device that are being clocked and that
will change state with every clock.

I already have a counter (that counts from 0 to 24) tied to the
incoming 6kHz clock. It is this counter that determines where I am in
the serial stream; and thus determines which flop within my data
register gets clocked with the incoming data.  But yes, I have already
thought about doing this.  But I don't need to--read below.





Building somewhat further on that approach, if the state machine
already has a signal that identifies the 'waiting for a new
transmission to occur' time, then you could gate that signal with the
counter being 0 and simply output a '1' when the protocol has been
broken.  That gives you one specific signal to monitor to trigger the
scope.

Either of those approaches though is only meant to give you a known
reliable trigger mechanism for a scope or logic analyzer so you can
investigate further (if it triggers) or reject your hypothesis (if it
does not).

It's also not really clear whether you have such a trigger condition
or if you're relying on perhaps some higher level system observation
instead.  Your original thought to build a pulse monitor was somewhat
along these lines, the problem with that approach though is that
you're jumping to a solution that has holes to it.  Even if your
hypothesis is correct you haven't actually verified the root cause
problem.

I did build the pulse monitor and the problem got worse.  This of
course told me that I must be fighting a timing that is on the hairy
edge, as there is a slight delay through my "filter".  So I started
looking at the path in much more scrutiny and found a section of the
placement that didn't have a lot of margin.  I tightened this up and
the problems have disappeared.  This obviously makes more sense since
I never saw any glitches/runts on the scope.  And it also explains why
some boards worked and some didn't.

Again, I appreciate the dialogue....

.

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