Re: Spartan3 SRL16 + SliceFF, LUT stability


"John_H":
Most precisely, the SRLs are designed to work with the local registers
without issue, adding one pipeline of delay. The LUT memories act
just like LUTs when the data has settled its shift; any changes to the
shift register tap value results in an immediate (Tlut delay) change
to the output without regard for the clock. When the clock edge
occurs, this settled value is latched in the FF (if you chose to use
it) before the shift data changes. It doesn't "buffer" the shift
register data, it delays it by a clock.

You're correct that if you're using both LUTs as shift registers, the
bx and by inputs are feeding the shift registers and cannot be used by
the flops for any other purpose. You can, however, have the output
from the shift register LUT separate from the accompanying register
allowing a separately clock-enabled version of the output strem to
exist with the always-enabled (from the mux-se4lect perspective)
version.

Thanks for making that clear.

I am using that module to implement a byte-stream buffer. Using
an up/down-counter, I can store 0..16 bytes in just 2 Spartan3 CLBs,
allowing 2-sided, fully sequential access (and avoiding the need for
doubled SliceM consumption for DualPort distributed ram).
It was a bit long-winded to make xst use the SliceL carry chain
for the counter, so with my posting here, I intended to minimize
things to think about, just in case some kind of debug should become
necessary.

Gruss

Jan Bruns



.

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