Re: Spartan3 SRL16 + SliceFF, LUT stability

Jan Bruns wrote:
Hallo.

When using a Spartan3 SliceM in 2x SRL16-Mode,
the Slice-FlipFlops and the SRLs must share the same clock
(and from the FPGA-Editor, it looks like if that clock's
polarity must be the same for both, SRLs and FFs).

Now, if I want to use the FFs (I don't think they can be
used for anything else then buffering the SRL's Output),
I'm not fully sure the FF clk will be early enough
to not sample the SRL during undefined output.

I think it's very likely that the FF clk is early enough,
but I don't see a way to ask the xilinx tools about that
(apart from the module attached compiles without errors
in ISE10.1 web).

Has anyone tried a simulation about this?
<snip>

Most precisely, the SRLs are designed to work with the local registers
without issue, adding one pipeline of delay. The LUT memories act
just like LUTs when the data has settled its shift; any changes to the
shift register tap value results in an immediate (Tlut delay) change
to the output without regard for the clock. When the clock edge
occurs, this settled value is latched in the FF (if you chose to use
it) before the shift data changes. It doesn't "buffer" the shift
register data, it delays it by a clock.

You're correct that if you're using both LUTs as shift registers, the
bx and by inputs are feeding the shift registers and cannot be used by
the flops for any other purpose. You can, however, have the output
from the shift register LUT separate from the accompanying register
allowing a separately clock-enabled version of the output strem to
exist with the always-enabled (from the mux-se4lect perspective)
version.

- John_H

.

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