problem about an interface between sfifo and sopc avalon MM slave

Hello !

I have created an interface between sfifo and sopc avalon MM slave.The
interface is just realized by define the avalon MM slave signals are
outside the niosii cpu. The 32x32 sfifo was created using altera
megafunction(optimzed by area,with overflow and empty protection),the
device i use ia cyclonII EP2C20. I define the IORD and IOWR macO(just the
same as the way to visit the avallon MM SLAVE component inside the nios
cpu) to write and read the sfifo in nios IDE, but i alwayse read zero, with
the embeded sigtap logic analyzer, ,i found the sinals from the avalon MM
slave interface which is outside the nios cpu are good(write,read
,chip-select,address,writedata),but the output of the sfifo(q and usedw)
are always zero,no matter the times that i write and read in nios IDE!!
I DON'T know why ,i need your help. please contact my eamil:
zhenyujiel@xxxxxxxxxxxx ,thank you!



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Relevant Pages

  • Re: JOP as SOPC component
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  • Re: JOP as SOPC component
    ... simply by only using SOPC Builder to create that Avalon slave device ... SOPC builder version. ... have the 'readdatavalid' signals implemented. ...
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    ... controllable by the slave) and whether the slave device has any read latency (and if it does, ... but e.g. for an SRAM interface there are some timings in ns. ... Avalon specification. ... your actions at the last cycle of the former transaction. ...
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  • Re: JOP as SOPC component
    ... slave implementation that follows the rule of Avalon: ... good question;-) It depends on the pipeline level. ... the original single cycle register at the first cycle ...
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  • Re: JOP as SOPC component
    ... The Avalon bus is very flexible. ... Now a very simple slave can be found at. ... the latency is the issue for JOP. ... I gather the only way the Cyclone ...
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