Re: More Actel 'Funnies'

That's the way I've been describing bus tri-states since I started
FPGA design 15 odd years ago. As far as I know it's a 'standard'
so the tools should be able to deal with it.
So have I but I've sometimes seen it not to work
Nicolas


Which doesn't fill me full of confidence in the Actel tools.


I tend to design at a very (too) low level and have been using 80MHz as
a 'standard' clock speed for about the last 10 years. My designs
tend to easily build & work with a simple clock constraint and
IO constraints. This has been the case with multiple designs in
Altera and Xilinx devices.

The design that ran at 66MHz in the Cyclone I (not a II) is struggling
to meet that in the Actel device, this is after removing some registers
to ease up the critical path.

I'm starting to look at Lattice devices, the first pass run in an
XP2 ran at 95MHz. This is without pin constraints, so it will be
slower then that but it looks much more like the performance I'm used to.



Nial


.

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