Re: Low frequency clock generation - need help

On Oct 2, 1:38 pm, KJ <kkjenni...@xxxxxxxxxxxxx> wrote:
On Oct 1, 4:33 pm, Svenn Are Bjerkem <svenn.bjer...@xxxxxxxxxxxxxx>
wrote:

Pulse shortener is made with one flip-flop clocked by sys_clk taking
qn to and with sys_clk. Both the counter and the pulse shortener is
clocked by the negative edge of sys_clk to have the clock enable
signal high when rising_edge on sys_clk happens. (Does using negative
edge (inverted sys_clk) need another clock buffer?)

No, but it is also unneeded and not helpful to use the negative edge
of the clock. You should be using the rising edge for the clock
enable, using the negative edge simply cuts down by 1/2 the max clock
rate that you can run the design at.

Shouldn't the enable mask be available well before and after the
rising edge of the system clock? I see no other possibility than to
use the negative edge to achieve this. What happens when there is skew
on the enable input related to the clock input on a ff due to wire
lengths?

I have no idea why you are using any DCMs for SPI. At the start you
said that you had implemented the counter and clock enable both
running off of the system clock. In any case, it is simple to add
whatever additional clock enables you may need.

What I meant was that the chip only has 2 DCM modules and 8 global
clock buffers. The synthesiser used all global clock buffers and
wanted more before I had integrated all my SPI modules. I then only
had the DCMs to spend, but they are assigned for other purposes in the
final design.

I think I have understood the benefits of using clock enable, both
through not having enough ressources and through different postings in
webforums, so I sat down and coded and coded but didn't really like
what I saw as a result.

What did you see? Why did you not like it?

When I looked at the code that I wrote to generate the two enables,
one for the spi clock toggling and one for the state machine, the
number of code lines were almost exceeding the number of lines in my
spi code. I am maybe too minimalistic since I come from ASIC full
custom design where I place my gates by hand. The synthesized logic
also looked larger than nescessary, but I think the mapper reduce
things for me "magically" when I generate the FPGA binary file. (I
still use ISE in noob mode)


I have searched on the net for some hours without finding any document
that really shows a best-practices solution on how to generate and use
clock enables for peripheral serial devices.

You didn't look too hard then. Symon reply also shows how to generate
and use the clock enables.

Symons code was a reply to my statement ....


I really wonder why. It
is not rocket science, is it?

Not rocket science, just simple sequential boolean logic.

I am in the transition from ASIC to FPGA. Re-learning threshold, you
know ....

--
Svenn
.

Relevant Pages

  • Re: Low frequency clock generation - need help
    ... decimation filter. ... to generate the divided clock by internal clock divider or clock ... Pulse shortener is made with one flip-flop clocked by sys_clk taking ... clock enables for peripheral serial devices. ...
    (comp.arch.fpga)
  • Re: Low frequency clock generation - need help
    ... I have currently been using a divided clock for spi-modules when I run ... Pulse shortener is made with one flip-flop clocked by sys_clk taking ... but it is also unneeded and not helpful to use the negative edge ... whatever additional clock enables you may need. ...
    (comp.arch.fpga)
  • Re: Low frequency clock generation - need help
    ... clocked by the negative edge of sys_clk to have the clock enable ... using the negative edge simply cuts down by 1/2 the max clock ... Then you are apparently new to digital logic design. ... whatever additional clock enables you may need. ...
    (comp.arch.fpga)
  • Re: Question about multi write ports RAM in FPGA?
    ... use clock enables to move the datapath pipeline forward every 1/3 fast ...
    (comp.arch.fpga)
  • Re: Mixed clocked/combinatorial coding styles (another thread)
    ... I don't consider my SPI code as finished but I've seen what ... of the SPI clock at the master where it *should* be for a normal SPI system. ... But does this choice force me to, for example, clock the CPU ... this clock frequency does not need to be used when communicating ...
    (comp.lang.vhdl)
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