Re: floating point round off errors

On Thu, 02 Oct 2008 19:14:28 -0800, glen herrmannsfeldt
<gah@xxxxxxxxxxxxxxxx> wrote:

Brian Drummond wrote:
At this point there are two aspects to consider:
....
(2) the importance of errors in the application anyway. (It may be worth
using higher precision internally in critical areas).

The nice thing about verilog implementations is that you
can easily add bits, even one or two. That is hard on a
processor with fixed sized registers.

Verilog and VHDL both.

How well would Verilog work for writing a high level model using actual
floats (not synthesisable), for comparison with the hardware
implementation? Make the testbench self-checking without external files.
That is the obvious approach to me in VHDL, but I don't know if it would
transfer to Verilog. However it is also not immune to problems of
precision; most VHDL implementations I've come across use double
precision but it isn't guaranteed. (So the testbench must also check
itself!)

If the Verilog implementation must be correct, you will need a reference
implementation in which every operation is known to be correct to single
precision (the difficult bit, in C!), and test for bitwise identical
results.

There might be some compilers that will force single precision
between every operation.

That would be useful. Otherwise you have to force the conversion
manually; possible but unnecessarily hard work.
- Brian
.

Relevant Pages

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