Re: Altera and DDR3

m wrote:
I've been told that Altera has patented I/O technology that makes DDR3
interfacing "better" (in quotes because that could mean anything). I
received this answer when I asked about DDR3 support since we are
considering migrating from Xilinx to Altera. The answer was that
Altera, due to this technology, is able to support DDR3 at 533MHz
clock rate while Xilinx seems to be tentative about 400MHz support.

What's the real story?

I don't know, but I can guess something. No idea, if this is even close,
haven't looked at Altera parts for awhile...

In DDR2 (and I suppose it's the same for DDR3) the memory chips have
On-Die-Termination (ODT), that can be turned on and off through a
dedicated IO. The idea is that you only turn it on when you send data
towards the memory chip, so there's a termination at the end of the
transmission line. The rest of the time the termination is turned off to
conserve power and avoid detrimental effects if you want to transmit the
OTHER way (i.e. from the memory chip to the controller, e.g. the FPGA).

Now, ideally this should be possible on BOTH sides, that is the
termination should be switchable on the side of the controller as well.
I know that in Xilinx devices this is not possible. DCIs are either
turned on or off permanently, it's "hardwired" in the bitstream. That
usually means that you burn tons of power and signal integrity is not
the optimum it could be.

Maybe recent Altera devices have the ability to turn off IO terminations
during operation? That would explain it and could be helpful.

That's my guess, for what it's worth. :)

cu,
Sean
.

Relevant Pages

  • Altera and DDR3
    ... I've been told that Altera has patented I/O technology that makes DDR3 ... Altera, due to this technology, is able to support DDR3 at 533MHz ...
    (comp.arch.fpga)
  • Re: DDR3 speed, Altera vs Xilinx
    ... We chose different paths:  Altera used hardened logic to get their ... We have DDR3 designs that are also working at 533 MHz. ... Even though Altera has some really mean, cool, and neat power point ...
    (comp.arch.fpga)
  • Re: DDR3 with Spartan-3
    ... spartan-3A DSP does not support DDR3-Voltage Levels. ... that Virtex-5 are the first FPGA's in production supporting DDR3 ...
    (comp.arch.fpga)
  • Re: Altera and DDR3
    ... Altera, due to this technology, is able to support DDR3 at 533MHz ... clock rate while Xilinx seems to be tentative about 400MHz support. ... To deal with the fact that each memory chip has a different clock ...  Dynamic on-chip termination ...
    (comp.arch.fpga)
  • Re: MEM_BAD_POINTER after SP2 installation
    ... and the fix worked for me: I uninstalled East Asian language ... problem with Microquill's SmartHeap application and is likely to occur under ... at app termination. ... updates on the status of this issue, please visit Microquill's support page ...
    (microsoft.public.windowsxp.basics)
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