Re: Moving to Altera from Xilinx

On Sep 15, 11:08 am, Jon Beniston <j...@xxxxxxxxxxxx> wrote:
On 15 Sep, 16:51, m <martin.use...@xxxxxxxxx> wrote:



I am interested to hear about experiences anyone may have had in
switching to Altera hardware and tools.

To be clear, the intent here isn't to start a "who's better" debate
but rather to understand what to expect from those who did switch,
regardless of the underlying issues.

In our particular case we'd be switching from V2 and V5 devices to
Arria and Stratix.  In general terms the applications involve image
processing.  I've seen Altera's approach to image processing IP and
tools and I have to say that I am impressed.  In contrast Xilinx's
image processing tools are more like a collection of app notes without
a real underlying structure.  The tools seem more user friendly...but
I don't have real experience with them yet.  I was surprised that
Altera discourages low-level design.  We've used low level
instantiation and explicit control of interconnect paths quite
effectively with Xilinx in order to squeeze performance out of modules
that needed it.  I suppose that there might be a point in trying to
stay high level in that designs have improved reusability and, if
chips are fast enough it really is better to avoid low-level work.

Certainly will help transitioning from X to A.

Jon

Our development group did a wholesale platform change from V2 Pro X to
Stratix II GX around 2-3 years ago, and it went very well. The change
was mainly due to the fundamental issues that we were having with
basic Xilinx IP blocks not working, as well as issues w/ the Rocket IO
in the Virtex 2 Pro X devices. What also helped is amount of local
support that we got from Altera (coupled w/ the lack of support from
Xilinx). In fairness to our local FAE, he was very good, but the way
priorities shake out amongst companies being supported locally, we
weren't the highest on the totem pole.

Anyways, we have not had a single errata or IP-based issue since the
switch. Everything has pretty much worked as advertised, and we have
been including plenty of the advanced DSP blockset modules in DSP
Builder / Simulink. It has taken some time to "cut our teeth" on the
DSP tools, but we haven't come across anything that we couldn't figure
out ourselves. We mainly use FIR filters and NCOs, so not much of the
image processing that you were asking about. With respect to your
comment about low-level design, the DSP builder tool really encourages
coming up with a high-level DSP design, which is then instantiated in
your project w/ a single component (typically using a .tcl script).
What I have found is that, in DSP Builder versions < 8.0, I needed to
do some manual massaging of the models in order to hit timing (the
Matlab simulations would work great, but then fail timing miserably in
place/route).

From what I understand, the 8.0 version of DSP Builder is a lot better
than the previous releases (takes care of timing, optimizing using
multi-cycle, etc), but we haven't upgraded, since we're in the middle
of a project right now. I definitely am looking forward to checking
out the new features, though.

One issue that I've been curious about is why these forums seem to be
dominated by issues people are having with Xilinx parts. From what I
understand, the market share is something like 60/30 between (Xilinx
and Altera, respectively), with the other guys cleaning up the rest.
I'm wondering why I don't see that sort of general trend in the posts
on here. Is it because people are going down other channels for
Altera support? Are there just more issues w/ Xilinx? Who knows.

Anyways, I just thought I would toss my $.02 worth.

Jeff
.

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