Re: need fast FPGA suggestions



John_H wrote:

You can feed a 500 MHz clock to a Spartan3 style device, use a divide-
by-2 in the DCM, and clock the output I/O blocks with the 250MHz clock
in DDR mode. You just need to handle the logic to deal with odd/even
starts and stops.

We don't need to distribute a 500 MHz clock, 250 or even 125 with LVDS would be fine.

I don't think you'll have power problems running only 32 channels of
13-bit counters but a power analysis will give you an idea of the
actual need (XPOWER tool?).

Spartan 3, huh? I'm just a little more comfortable with that, as I just did a migration to Spartan IIE (always on the trailing edge!) I can even get those in TQFP's, which I can mount and rework myself. I'm avoiding BGAs.

I will have to look into the implications of using Spartan 3E on this.
If the counters are running at 250 MHz, then the granularity of timing timing settings is 4 ns, which may well be tolerable. If they need finer resolution, then there are ways to fudge that with the DDR.
So, you think a 13-bit counter feeding a 13-bit identity comparator will work at 250 MHz? (I've never pushed the speeds on these FPGAs at all, all of by previous projects were very relaxed by comparison, like 40 MHz.)

The counters are simple. The DDR is straightforward. The boundary
conditions are limited.

If you want better than 2ns resolution, you can use the SERDES
channels on a Virtex-5FX style part (much more expensive) and hit
resolution under 300ps; a nice option for a piece of test equipment
where one-up price is of little consequence compared to the
engineering time but harder to swallow for production.

Yeah, I really don't think we can handle $2000 IC's. This isn't a real production project, we might build 5 of them at a time, but we are still cost-sensitive.

Thanks,

Jon

.

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