Re: why does inferred RAM cause synthesis times to explode?

On Tue, 19 Aug 2008 10:15:50 +0100, Jonathan Bromley wrote:

ISE 8.2 (yeah, I know it's ancient, but I haven't got
around to installing anything newer yet) just locked-up
with 100% CPU usage, presumably because it failed to
infer the RAM from my description and was trying to
build a gazillion registers instead. Must go look up
the correct inference templates for XST :-)

Ahah! Got it...

XST User Guide is a bit woolly about Verilog
RAM inference. It turns out that this form is OK:

always @(posedge clock)
if (enable) begin
if (write) begin
mem[address] <= write_data;
read_data <= write_data ;
end else begin
read_data <= mem[address];
end
end

but this form is not - it hangs XST:

always @(posedge clock)
if (enable) begin
if (write) begin
mem[address] = write_data;
end
read_data <= mem[address];
end

Despite what it says in the XST user guide, it seems
that the same story applies in VHDL: the memory store
must be a signal.

Have I missed something?
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
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