Re: Block Rams

On Aug 11, 8:44 am, John_H <newsgr...@xxxxxxxxxxxxxxxx> wrote:

Where else can one get information directly from a bona-fide expert on
FIFOs?
Thanks again for being here, Peter.

Hi, John.
Is this what you had in mind?

FIFOs, a tutorial description by Peter Alfke 8-11-2008
A FIFO is a sequential data buffer that is very easy to use:
Write a sequence of data words into the FIFO, and read them out in the
same sequence. Writing and reading can overlap. There is no explicit
addressing.
Most practical implementations use a dual-ported memory (RAM), writing
into one port, addressed by the write counter, and reading through the
other port, addressed by the read counter. This allows the use of two
totally independent clocks for write and read. This is often called
asynchronous operation, although writing as well as reading are each
synchronous operation in their respective clock domain.

Most FIFO designs require free-running clocks, where the write or read
operation is controlled by the respective clock enable. A typical FIFO
has a DATA IN bus, a DATA OUT bus, a free-running write clock with its
Enable control, and a free-running read clock with its Enable control.
Such a FIFO is very easy to use, since it hides all functional and
timing complexity from the user.

FLAGS:
The FIFO uses an EMPTY flag to signal to the user that no more read
operations should be started. At other times the FULL flag can tells
the user that no more write operation should be started.
Generating these flags requires that the two addressing counters be
compared for equality (identity), although they are incremented by two
independent clocks. This is a very tricky operation. To avoid
uncontrolled asynchronous decoding spikes, the counters usually count
in a Gray sequence, where only one bit changes on any increment.
And the two clocks can interact and might cause metastable delays.
Even more complex is the decoding of Almost Empty and Almost Full
conditions, especially when their offset values are programmable.
The user is isolated from all these complexities, but must accept
certain timing ambiguities. The Full and Empty flags will always go
active exactly on-time, to stop further reading or writing, but these
flags must of necessity be allowed to take several clock periods to go
inactive again.
When the first word is being written into an empty FIFO, Empty goes
low, and waits for an enabled read clock to present the Data on the
DATA OUT bus.
There is a special mode of operation, called First Word Fall Through
(FWFT), where the first word written into the empty FIFO directly, on
its own, appears at the DATA OUT port.
The conventional mode can be called Pull, while FWFT can be called
Push. The two modes differ only in their response to the first write
into an empty FIFO.
The preceding described the most demanding case of a high-speed dual-
clock (asynchronous) FIFO. In the special case where both clocks are
identical (even if individually enabled) the internal decoding is much
simpler, and the binary counters and the control can be designed like
a synchronous state machine.
At low clock rates, the two clocks can be synchronized to each other,
or the read and write operations can be time-multiplexed in a single-
port memory.
Very small FIFOs can be implemented with flip-flops or register
arrays, sometimes even with shift registers.


.

Relevant Pages

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