Re: Downsizing Verilog synthesization.

On Aug 7, 2:57 pm, Jim Granville <no.s...@xxxxxxxxxxxxxxxxxxxxxx>
wrote:
David Tweed wrote:
eromlignod wrote:

The incoming signals are square waves at the fundamental frequency of
each of the 219 strings in the piano that are being magnetically
sustained (vibrate forever).  I only read 44 strings at a time, tune
them, then go on to the next 44, etc.  So there are 44 counting
modules and an output address signal to instruct the sustainer
circuits when to vibrate the next string.

I first convert the wave to a "period" wave that has an "on" time
equal to one period of the string's vibration.  I then use this wave
to enable counting of the 50-MHz system clock.  So I get a count of
how many clock ticks of the system clock occur for one period of
string vibration.  This takes up to 21 bits for the low strings.  I
average 32 of these numbers and calculate an error based on a stored
setpoint.  Currently I'm using a theoretical setpoint, but eventually
I will want to add the feature whereby a piano tech can hand-tune the
piano and then "store" his tuning numbers for subsequent use.

There is flaw in this approach, which is the Signal to Noise
of a SINGLE cycle. With 44 going off at once, you will have crosstalk.
That 21 bits will be mostly an illusion.

Ah, this makes what you are doing much clearer.

One immediate suggestion would be this: Rather than using 44 separate
50-MHz counters, use just one counter and 44 registers that capture
the value of that counter when the rising edge of the input occurs.

Then, you have a module that scans those 44 latches, and each time
one is updated, you subtract the previous value from the current value
(mod 2**21) to get the period for that string. This should save a lot
of chip resources, converting lots of slice flip-flops into block RAM.

The "previous values" can be stored in block RAM, the calibration
periods can be stored in block RAM, the PWM values can be stored in
block RAM, etc. Everything except for the 44 latches can be processed
sequentially rather than in parallel.

Even simpler, since you KNOW what frequency you want, set up
a pair of Loadable counter, close together as MIN as MIX and generate a
TuneUP and TuneDOWN signal from when outside this error band.

- drive those into LEDS and your Tune motors.

Then your datapaths are just the error signals.

Read up on reciprocal Frequecy counters, these give higher
precisions by counting a time for a certain WHOLE number
of cycles.
To do that, you would preload 3 numbers, the Min/Max counts, and
the cycles to total over. Much better signal to noise.
You might even get the whole thing working in a Block Ram,
as you can lower the 50MHz...

You don't want the pianist saying your system is crap do you ;)

-jg- Hide quoted text -

- Show quoted text -


An ordinary frequency counter is not an option in this application.
The lowest note A0 in a piano is 27.5 Hz and I need an accuracy of
less than one "cent" (1/100th of a musical semitone). One cent sharp
at 27.5 Hz is

27.5 * (2**(1/1200)) = 27.5159 Hz

That's a difference in frequency of .0159 Hz. To be able to count
with this accuracy would require that I count for at least a minute to
get each reading. This is unacceptable.

Also, please read the publicity I posted the links to, or the patent
(6,559,369). I do not use any moving parts to control the string's
pitch.

Don
Kansas City
.

Relevant Pages

  • Re: Downsizing Verilog synthesization.
    ... The device is a self-tuning piano. ... I only read 44 strings at a time, tune ... circuits when to vibrate the next string. ...
    (comp.arch.fpga)
  • Re: Downsizing Verilog synthesization.
    ... The device is a self-tuning piano. ... I only read 44 strings at a time, tune ... circuits when to vibrate the next string. ...
    (comp.arch.fpga)
  • Re: Downsizing Verilog synthesization.
    ... I only read 44 strings at a time, ... circuits when to vibrate the next string. ... I will want to add the feature whereby a piano tech can hand-tune the ... converting lots of slice flip-flops into block RAM. ...
    (comp.arch.fpga)
  • Re: Downsizing Verilog synthesization.
    ... each of the 219 strings in the piano that are being magnetically ... circuits when to vibrate the next string. ... I will want to add the feature whereby a piano tech can hand-tune the ... converting lots of slice flip-flops into block RAM. ...
    (comp.arch.fpga)
  • Re: Self-Tuning Piano
    ... Are you a piano tuner or one that is familiar with ... some basic work with tuning - and am told I could, ... My dad started piano servicing in 1965 and my family grew up in the ... of strings that all need to vibrate to the correct scale. ...
    (rec.music.makers.piano)