Re: how to change the system clk in EDK project



On Aug 7, 2:14 pm, John McCaskill <jhmccask...@xxxxxxxxx> wrote:
On Aug 7, 3:40 am, fmostafa <fatma.abouele...@xxxxxxxx> wrote:

hi all;

I have a question about the system clk in EDK project, my processor
clk is 100 Mhz and my bus clk is 25Mhz , i tried to increase the bus
clk to 50 Mhz , i did this by changing in the DCM , as i changed
the CLKDV divisor to 2 instead of 4 , which means as i thought
(100/2) instead of (100/4), and cleaned the hardware and i stared to
generate the netlist and the bitstream but i don't know the uart is
not working in a right way , and of course i couldn't examine the rest
of the system .
i don't know if what i did is right or there is something missed or
there is another way to change the frequency.

thanks
fatma

There are several cores that need to have their parameters updated
when you change the OPB/PLB bus speed.

The UART lite is one of these cores. It has a parameter C_CLK_FREQ
that needs to be set to the new frequency. You can change it in the
MHS file, or from the Configure IP GUI window under system/OPB.

There are other cores that need to be updated as well. I don't have a
complete list of the, but serial IO cores, such as the UART and SPI
cores, tend to generate baud rates or external clocks from the bus
clock.

Regards,

John McCaskillwww.FasterTechnology.com

hi John;
thanks for your reply , but i have another question in the
plb_bram_if_cntlr i think that i have to change the c_plb_period_ps, i
can't understand how to change this parameter.

BEGIN plb_bram_if_cntlr
PARAMETER INSTANCE = plb_bram_if_cntlr_1
PARAMETER HW_VER = 1.00.b
PARAMETER c_plb_clk_period_ps = 20000
PARAMETER c_baseaddr = 0xfffe0000
PARAMETER c_highaddr = 0xffffffff
BUS_INTERFACE SPLB = plb
BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_port
END

thanks
fatma
.



Relevant Pages

  • Re: Referenced signal not in sensitivity list
    ... The function I am implementing is a FIFO that reads data from the bus ... when clk and work_in are both high. ... the book presents the design of a complete RISC ... A typical function that you're trying to implement wants to clock data ...
    (comp.lang.verilog)
  • Doubt about SystemVerilog tasks in interfaces
    ... I have created an interface for a certain bus. ... endmodule // testmod3 ... interface bus(input clk); ...
    (comp.lang.verilog)
  • Re: how to change the system clk in EDK project
    ... when you change the OPB/PLB bus speed. ... complete list of the, but serial IO cores, such as the UART and SPI ... If you want the PLB clock to be 50 MHz, ... want to know it for DRC or constraint generation. ...
    (comp.arch.fpga)
  • Re: 50 cores
    ... number of cores. ... on a bus because while A and B are talking, ... overflow exploits, no more crashed OSs, no more memory leaks. ... The trick to making it go fast is to sort chunks that will ...
    (sci.electronics.design)
  • Re: Multiple components driving a single bus
    ... Let's say I've got 2 blocks that can drive one bus (but there could be ... port map (CLK => CLK, ... ADDR => ADDR, ...
    (comp.lang.vhdl)