how to change the system clk in EDK project

hi all;

I have a question about the system clk in EDK project, my processor
clk is 100 Mhz and my bus clk is 25Mhz , i tried to increase the bus
clk to 50 Mhz , i did this by changing in the DCM , as i changed
the CLKDV divisor to 2 instead of 4 , which means as i thought
(100/2) instead of (100/4), and cleaned the hardware and i stared to
generate the netlist and the bitstream but i don't know the uart is
not working in a right way , and of course i couldn't examine the rest
of the system .
i don't know if what i did is right or there is something missed or
there is another way to change the frequency.