Microblaze to LCD module via FSL bus
- From: "Ray D." <ray.delvecchio@xxxxxxxxx>
- Date: Tue, 5 Aug 2008 12:50:39 -0700 (PDT)
Hello all,
I've been having trouble with this for a while, but I think I'm
extremely close to getting something working. I currently am using a
Spartan-3E starter board with an LCD. Before I was building a system
purely with VHDL, but I want to add a MicroBlaze core and connect my
hardware LCD module to the FSL bus instead of implementing software
drivers. The interface and description of the LCD module are shown
below:
entity LCD_top is
Port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
din : in STD_LOGIC_VECTOR (7 downto 0);
din_ready : in STD_LOGIC;
busy : out STD_LOGIC;
LCD_D : out STD_LOGIC_VECTOR (11 downto 8);
LCD_E : out STD_LOGIC;
LCD_RS : out STD_LOGIC;
LCD_RW : out STD_LOGIC);
end LCD_top;
The busy signal is set high the entire time data is being
written to the LCD. If busy = 0, then I set din_ready high and set
the 8-bits of
data. This is buffered within the LCD module and you only need to
hold din_ready for a single cycle to write to the LCD. The LCD is
connected over a 4-bit interface to the FPGA and this is taken care of
within the LCD module. When the writing operation begins busy is set
to '1' until complete.
Within Platform Studio I imported this module using the 'Create and
Import Peripheral' wizard. This generated the FSL wrapper file to
interface with the FSL FIFO. I instantiated my module as a component
within this wrapper. I also added the necessary output ports to drive
the external LCD on the board. The top level interface file is shown
below:
entity lcd_core is
port
(
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add or delete.
FSL_Clk : in std_logic;
FSL_Rst : in std_logic;
FSL_S_Clk : out std_logic;
FSL_S_Read : out std_logic;
FSL_S_Data : in std_logic_vector(0 to 31);
FSL_S_Control : in std_logic;
FSL_S_Exists : in std_logic;
LCD_D : out std_logic_vector(0 to 3);
LCD_E : out std_logic;
LCD_RS : out std_logic;
LCD_RW : out std_logic
);
attribute SIGIS : string;
attribute SIGIS of FSL_Clk : signal is "Clk";
attribute SIGIS of FSL_S_Clk : signal is "Clk";
end lcd_core;
architecture structure of lcd_core is
component lcd_top
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
din : in STD_LOGIC_VECTOR (7 downto 0);
din_ready : in STD_LOGIC;
busy : out STD_LOGIC;
LCD_D : out STD_LOGIC_VECTOR (11 downto 8);
LCD_E : out STD_LOGIC;
LCD_RS : out STD_LOGIC;
LCD_RW : out STD_LOGIC);
end component;
signal dataIn : std_logic_vector(7 downto 0);
signal dataInReady : std_logic;
signal LCD_busy : std_logic;
type statetype is (S1, S2, S3);
signal state, next_state : statetype := S1;
begin
M1: lcd_top port map(FSL_Clk, FSL_Rst, dataIn, dataInReady, LCD_busy,
LCD_D, LCD_E, LCD_RS, LCD_RW);
state <= next_state;
process(FSL_Clk, FSL_Rst) is
begin
if(FSL_Rst = '1') then
next_state <= S1;
FSL_S_Read <= '0';
dataInReady <= '0';
test_out <= '0';
elsif(rising_edge(FSL_Clk)) then
case state is
when S1 =>
FSL_S_Read <= '0';
if (FSL_S_Exists = '1') then
dataIn(7 downto 0) <= FSL_S_Data(24 to 31);
dataInReady <= '1';
next_state <= S2;
end if;
when S2 =>
dataInReady <= '0';
next_state <= S3;
when S3 =>
if (LCD_busy = '0') then
FSL_S_Read <= '1';
next_state <= S1;
end if;
end case;
end if;
end process;
end architecture structure;
I have successfully downloaded this design to the board and believe I
have all the correct port connections. The software application is
very simple and the main loop is shown below:
while(1)
{
// Simple delay loop to allow for LCD initialization
procedures in hardware
do
{ i++;}
while(i < 25000000);
printOnce = TRUE;
// write a single character to the LCD
if(printOnce == TRUE && donePrinting == FALSE)
{
LCD_data = 0x42000000;
putdfslx(LCD_data, 0, FSL_DEFAULT);
fsl_isinvalid(isInvalid);
if(isInvalid == 1)
print("Invalid Operation!\r\n");
else
print("Valid Operation!\r\n");
donePrinting = TRUE;
}
}
First, my LCD peripheral is setup as a slave to the FSL bus while the
microblaze processor core is the master. With that said, are the
putdfslx() or putfslx() functions the correct way to pass data to the
LCD core? Based on my previous descriptions of my system, does it
seem as though this is implemented correctly? It runs and outputs
'Valid Operation', but the LCD is not reponsive whatsoever. I have
already tested this module before and had it working properly without
MicroBlaze. I also added a test_out port to lcd_core (interface
file), and mapped this to an unused pin on the Spartan board. This
output pin was set to '0' upon reset and then set to '1' permanently
if S3 was reached as shown below. I have confirmed that this state is
reached because the pin was indeed set high.
when S3 =>
if (LCD_busy = '0') then
test_out <= '1';
FSL_S_Read <= '1';
next_state <= S1;
end if;
Any idea as to why this might not be working? Am I missing some type
of software initialization of the FSL bus? I already had a response
saying you can directly connect the module to the FSL master interface
on Microblaze without going through the bus, but in the future I made
need to add several peripherals so I would kind of like to get this
working with the bus if possible. I GREATLY appreciate any input.
Thank you!
.
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