Re: Fixed point number hardware implementation
- From: "kami" <kamran.wadood@xxxxxxxxxxx>
- Date: Thu, 31 Jul 2008 11:36:45 -0500
Hi there,
I already have the fixed point values for the integers and as they're just
5 coefficients, I have just taken them as constants. Do you think it is
alright? Well, then I am giving input(16-bit {1 sign bit and 15 fractional
bits}) from the switches and buttons on the Spartan-3 board. As there are
just 4 1-bit push buttons and an 8-bit switch (12-bits altogether, and then
I am keeping 4 bits constant). Then the output is also 16-bit which
includes 1 sign bit, 4 integer bits and 11 fractional bits. Now, I have
used the 7-segment display to show the output in such a way that the
leftmost digit is showing the hex value of 4 integer bits, and then a dot
to show decimal point and then the next 3 digits for fractional part but
as there are 11-bits in fractional part, so, I have padded a zero at the
end of fractional part just to make it a 4-bit value for the hex-decoder.
And then I am using the last dp (dot/decimal point on 7-seg display to
indicate the sign of the number).
So, I am only giving input from the board and getting the output and not
using any RAM/ROM or multiplier blocks, I have only used constants and the
operators ('+', '-', '*') and left it all to the VHDL to do all the
intermediate arithmetic and use the hardware components as required, will
it be fine?
Do you think it is a good design?
Now, I was wondering what will be the best option if I wanted to
demonstrate the filter operation more clearly. I mean these are just
numbers that I am showing on the 7-seg display. But if I want to give a
sinusoidal input and get a filtered waveform at the output.
1)I have got the code for vhdl sine generator.
2)Showing the ouput on the oscilloscope? it sounds a bit tedious.
3)Do you think interfacing a microphone and speaker would work for this
design (and for Spartan-3)?
4)Or giving the output back to the simulator and showing the waveform
would do?
5)or any other application/test case you would suggest for IIR filter
implementation on FPGA?
Thanks very much for your help.
Regards,
Kami
.
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