Re: XAUI - INTERNAL LOOPBACK SETUP - DRP (DYNAMIC RECONFIGURATION PORT)

On Jun 24, 9:49 pm, explore <chethanzm...@xxxxxxxxx> wrote:
Hello Austin,
Thanks for responding.

This is for a Virtex 5 LX110t device on a Avnet PCIE board AES-XLX-
V5LXT-PCIE110-G. I am trying a near-end PMA serial-loopback just
because the xaui core came with this default setting. For now I have
been following the instructions provided in UG196 about loopback modes
(chapter 9 in UG 196). Mainly, my task here is to control the
loopback externally (through the device driver). The verilog code that
controls the loopback as it came with xaui v7.2 is as follows.

assign loopback_int = mgt_loopback ? 3'b010 : 3'b000;

mgt_loopback is an output from the xaui core (the 'blackbox'). The
near-end PMA loopback("010") is enabled if mgt_loopback is high. The
mgt_loopback can be set high through the DRP or the MDIO interface as
suggested in the user-guides (UG196 and UG150). My issue specifically
is to know how these DRP ports can be configured in order to setup an
internal loopback and control it through my device driver.

I would be happy to know your suggestions on this.

Thanks,
Chethan

On Jun 23, 6:08 pm, austin <aus...@xxxxxxxxxx> wrote:> Chetan,

What device family? V2P, V4, or V5?

Also, there is a serial loopback, and a parallel loopback. And, if that
is not enough, are we talking near end, or far end which is looping back?

Generally, a parallel or digital loopback checks the function and the
logic (step one of any testing). Then a near end serial loopback will
check the analog side. Often the serial loopback must have a good
transmit termination, as reflections may cause errors. In this sense,
looping back with nothing connected may fail due to reflections (get out
the scope). Following that, looping back the far end on its parallel
side will successfully check the analog and digital of the near end, and
the analog looped back at the far end. Then the only thing not checked
is synchronization (far end clock vs near end clock). For testing the
clocking, you need a mode at the far end to use either the local clock,
or to re-use the received clock. If you use the far end local clock,
then you also need a loopback at the far end after the receive FIFO,
before the transmit FIFO so that all of the design is tested.]

Loopback testing can be a major task:

http://www.juniper.net/techpubs/software/junos/junos76/swconfig76-net...

http://www.credence.com/technical-library/open-docs/test-trends_loopb...

Austin

hey dude.though it is difficult but you need not to suffer in
loopback using DRP use the coregen create ur own top module with the
generated GTP rocketIO instantiation file.In that file modify the
value of the parameter called loopback to 001 for pcs loopback ,010
for pma loopback and 000 for normal operation.( these are all near end
loopbacks).i already finished these things and tested them.Now i am
working on the far end loopbacks.
.

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