Re: Simple 8253
- From: "Symon" <symon_brewer@xxxxxxxxxxx>
- Date: Thu, 31 Jul 2008 10:20:37 +0100
if write = '1' then
irq <=0;
reload <= dbus;
elsif falling_edge(clock) then
if counter = 0 then
counter <= reload;
irq <= '1';
else
counter <= counter - 1;
irq <= '0'; -- AUTO EOI
end if;
end if;
I know I shouldn't do homework for people but what the hey. Use the write
signal as an asynchronous reset. Also, use numeric.std . It's lovely.
http://www.synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdf
HTH, Syms.
.
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