Re: Die sizes of FPGAs (approx)

On Jul 29, 5:54 am, "Simon Heinzle" <shein...@xxxxxxxxxxx> wrote:
Hi comp.arch.fpga,

I am doing a little research on die sizes, mainly because I want to argue
how much you have to trade hardware flexibility against die size. The second
point is, I'm just curious if FPGAs are still the biggest high-volume ICs on
the market or if they are already beaten by NVIDIAs newest GT280 GPU (which
has about 576 square mm at 65nm).

I haven't found anything useful on the web yet, that's why I am asking here.
What are the approximate die sizes of the state-of-the-art high density
FPGAs? (For exampe Virtex5 XC5VLX220, LX330 or SX240T, and the Stratix IV
EP4SGX360, SGX530, SE530 or SE680?

Thanks in advance!

Best regards,
Simon

There are many aspects:
Technology (Moore's Law) reduces the min feature size by the square
root of 2 every 2 years, now perhaps every 3 years, thus doubling the
transistor count per area each time.
Architecture tries to make best use of the additional transistors
Chip Circuit Design and lay-out comes up with the most efficient
implementation
Manufacturing is constrained by the reticle size, and by the "defect
density", to achieve reasonable yield and thus acceptable cost at the
high end.
As a result, the very largest FPGAs are around 25 mm square, or 600+
square millimeters. That has not changed for many years.
There is always a strong user demand for the largest possible FPGAs. I
think it's from all those users who really wanted something even
bigger, even at a higher price. We have observed that "high demand at
the high end" ever since the X3090 in 1988. Its logic resources were
almost exactly 1000 times less than those of the newest top-end
Virtex-5 devices.
Moore's Law in action ! And the density increase will continue...
Peter Alfke
.