Re: Additional Hardware Module with Xilinx MicroBlaze Processor

On Jul 25, 3:22 am, "Göran Bilski" <goran.bil...@xxxxxxxxxx> wrote:
Hi,

A pcore in EDK contains the HDL files and a set of data files.
All files are in ASCII format.
The hdl files is in pcores/<your module>_vX_XX_a/hdl/vhdl
The data files is in pcores/<your module>_vX_XX_a/data

There are two data files that you need.
First the .pao file which contains a the list of HDL files that your module
need.
It can contain reference to other pcores libraries if needed
The second is the .mpd files which contains all information XPS needs.
It contains: type of core, what bus interfaces exists, which
parameters/generics, signals,..

There is a document in the installation describing these files, the data
files is called PSF files.
When you use "Create and Import Peripheral" it creates the data files for
you.
You can also look in existing pcores to see what they contains.

The fit_timer in EDK is very simple and should give you a hint how to create
a pcore for your LCD module.
You don't need any bus interfaces, just pure signals.

Göran

"Ray D." <ray.delvecc...@xxxxxxxxx> wrote in message

news:61bf0515-e8b9-44fb-9e8f-268ca7ed6bca@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
On Jul 24, 2:44 am, "Göran Bilski" <goran.bil...@xxxxxxxxxx> wrote:



Hi,

You don't need the FSL_bus.
You can directly take the MicroBlaze signals FSL0_M_Data, FSL0_M_Full,
FSL0_M_Write and connect them to your module.
If you want to do this in EDK, you will need to create a pcore for your
module and manually connect these signal in XPS.
You can also make these signal external to the EDK project and connect
them
in Project Navigator.
It's depend on how your design look now.

Göran

"Ray D." <ray.delvecc...@xxxxxxxxx> wrote in message

news:0b840fac-04c0-41a6-8ca1-99593fe48018@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
On Jul 23, 3:26 pm, "Ray D." <ray.delvecc...@xxxxxxxxx> wrote:

On Jul 22, 2:34 am, "Göran Bilski" <goran.bil...@xxxxxxxxxx> wrote:

Hi,

Then it should be a direct match for the FSL interface.
If MicroBlaze executes a 'put' instruction , it will not write until
the
FSL_M_Full flag is '0' and when it write it will set the FSL_M Write
high
for one clock cycle.
MicroBlaze have plenty of options for the FSL instructions, you can
get
all
about them in the reference manual.

Göran

"Ray D." <ray.delvecc...@xxxxxxxxx> wrote in message

news:693f947e-929e-49f6-939d-d834e0048121@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
On Jul 21, 2:36 am, "Göran Bilski" <goran.bil...@xxxxxxxxxx> wrote:

Hi,

Depending a little on how your busy signals work, you might just
hook
up
your module to the FSL interface on MicroBlaze.
Your busy signal needs be high when it can't accept a new word even
when
there is no attempt to write to the module.
MicroBlaze will also just do one cycle write so your module needs to
accept
a new word in one clock cycle when busy is low.

Connect:
din(7 downto 0) -> FSL0_M_Data(24 to 31)
din_ready -> FSL0_M_Write
busy -> FSL0_M_Full

You need to enable FSL Interfaces to MicroBlaze with the parameter
C_FSL_LINKS (set it to 1)
You can write to the fsl interface with the function putfslx, you
can
read
more about this function in the document "OS and Libraries Document
Collection".

Göran

"Ray D." <ray.delvecc...@xxxxxxxxx> wrote in message

news:276dce6d-c9ed-4937-95ea-e3c86ff3656a@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx

Hey all,

I have a Xilinx Spartan-3E starter board, and I'm implementing a
MicroBlaze processor on the FPGA. I would also like to use the
LCD
which is on board, and I have already developed a hardware module
that
takes care of initialization and printing to the LCD. The
interface
is shown below:

entity LCD_top is
Port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;

din : in STD_LOGIC_VECTOR (7 downto 0);
din_ready : in STD_LOGIC;
busy : out STD_LOGIC;

LCD_D : out STD_LOGIC_VECTOR (11 downto 8);
LCD_E : out STD_LOGIC;
LCD_RS : out STD_LOGIC;
LCD_RW : out STD_LOGIC

);
end LCD_top;

I really would like to instantiate this module along with the
processor core. My question is this - how would I go about
interfacing this with the MicroBlaze processor internal to the
FPGA?
What I would like to do is define a GPIO port on the processor to
connect to the din, din_ready and busy lines of the LCD module,
but
I
keep getting the following error:

ERROR:MDT - INST:LCD_data_status_10Bit PORT:GPIO_IO
CONNECTOR:LCD_data_status_10Bit_GPIO_IO - C:\EDK_Test_LCD
\system.mhs line 150
- connection is not connected to an external port!
MPD subproperties IOB_STATE=BUF|REG or THREE_STATE=TRUE require
that the port
be connected directly to an external port.

Is there any way to work around this? I realize I could just
connect
the LCD to the GPIO directly and write software drivers, but I'm
trying to avoid that because I already have the hardware module in
place and working smoothly. It will also be nice to have this
separate module so that it does the work of printing to the LCD,
and
the processor itself can stay busy with other more important jobs.

Also, is there an easier way to add another hardware module
without
manually editing the generated VHDL files for the core? I'm not
sure
if you can do that within Platform Studio.

Any advice would be much appreciated, thanks!

Ray

That is how the module works so I'll have to try some of these
options! The busy signal is set high the entire time data is being
written to the LCD. Originally I had a module "program.vhd" that
controlled the LCD module along with a keyboard module that we we had
in place for user input. Within program.vhd, I implement a state
machine and check if the busy signal is high before writing to the
LCD. If busy = 0, then I set din_ready high and set the 8-bits of
data. This is buffered within the LCD module and you only need to
hold din_ready for a single cycle to write to the LCD. The LCD is
connected over a 4-bit interface to the FPGA and this is taken care of
within the LCD module. When the writing operation begins busy is set
to '1' until complete.

Ray

OK - I'm new to using the EDK and am having trouble implementing this
with the FSL bus. I have a few questions:

1) When I create a custom peripheral, it generates an HDL wrapper - Do
I simply edit this wrapper by instantiating my LCD_top module as a
component within the top level design?

2) Should I check the box "Generate template driver files to help you
implement software interface", or will the provided functions to read
and write to the FSL bus suffice?

3) Do you know of any good tutorials on how to implement a custom
peripheral on the FSL bus? I've come across a few for adding
peripherals to the other buses, but most that I have found do not
follow through with how to edit the VHDL files and correctly add the
peripheral to the system in Platform Studio (they simply tell you go
to 'Create/Import Custom Peripheral').

Any help/input is appreciated, thanks!

Ray

Two more things -

1) the four output ports of the LCD module must be connected to the
external FPGA pins in order to drive the LCD. What is the best way to
go about doing this? Is this something that can be edited within
Platform Studio or do I need to manually edit VHDL/UCF files? I'm
assuming I will have to add the outputs to the interface shown below.

2) When I choose the master interface for the FSL bus, the ports are
defined as follows:

-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add or delete.
FSL_Clk : in std_logic;
FSL_Rst : in std_logic;
FSL_S_Clk : out std_logic;
FSL_S_Read : out std_logic;
FSL_S_Data : in std_logic_vector(0 to 31);
FSL_S_Control : in std_logic;
FSL_S_Exists : in std_logic;
FSL_M_Clk : out std_logic;
FSL_M_Write : out std_logic;
FSL_M_Data : out std_logic_vector(0 to 31);
FSL_M_Control : out std_logic;
FSL_M_Full : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------

You mention that my din(7 downto 0) port should be connected to the
FSL_M_Data port, but the former is an input while the latter is an
output. Am I missing something? I tried to define this as a slave
interface, but that also yields an error when I try to generate the
bitstream.

Thanks.

I think I understand what you are saying, but I'm still unsure of how
to implement it. I went through the 'Create and Import Peripheral'
wizard to create the pcore and HDL wrapper file, but when you go
through this it asks which bus you wish to attach the peripheral to -
this generated HDL file is an interface file for the FSL bus,
correct? I assumed I needed to edit this file and place my LCD module
within this interface file (with the interface shown in my previous
message). Do I need to go through this wizard to directly connect to
the FSL interface or is this the incorrect method?

When you say directly take the MicroBlaze signal and connect them to
my module, do you mean edit the aforementioned wrapper ...

read more »


Göran ,

I feel as though I'm very close to implementing this, but still have
some questions (hopefully my last few questions!) - I'll first
document the steps I have taken:

- I implemented my module as a pcore by using the 'Create and Import
Peripheral' wizard - this generated the HDL wrapper file as an FSL bus
interface (is that correct?). I deleted this file and simply imported
my two VHDL LCD files (LCD.vhd, LCD_top.vhd - LCD.vhd is an internal
component of LCD_top.vhd) into this directory.

- I then edited the MPD file to look as shown below. As you can see,
I commented out the bus interface specifications since there should be
no FSL bus connection and edited the port declarations. I also added,
but commented an IO_INTERFACE.

BEGIN lcd_core

## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION HDL = VHDL

## Bus Interfaces
##BUS_INTERFACE BUS=SFSL, BUS_STD=FSL, BUS_TYPE=SLAVE
##BUS_INTERFACE BUS=MFSL, BUS_STD=FSL, BUS_TYPE=MASTER

#IO_INTERFACE IO_IF = lcd_0

## Peripheral ports
PORT clk = "", DIR=I, SIGIS=Clk
PORT reset = "", DIR=I, SIGIS=Rst
PORT din_ready = "", DIR=I
PORT din = "", DIR=I, VEC=[0:7]
PORT busy = "", DIR=O
PORT LCD_D = "", DIR=O, VEC=[8:11]
PORT LCD_E = "", DIR=O
PORT LCD_RS = "", DIR=O
PORT LCD_RW = "", DIR=O

END

- I edited the PAO file to include my two VHDL LCD modules (LCD.vhd
and LCD_top.vhd), and removed the wrapper file that was originally
there by default when created.

- In the 'Project Information Area', I added the user IP module from
the 'IP Catalog' tab

- In 'System Assembly View', and the 'Ports' tab, I expanded the core
and made the four LCD_x outputs external ports. Now I'm assuming this
is where you must connect the remaining signals to the FSL interface,
but I don't know how. I choose the option 'New Connection', but this
simply edits the MHS file port name. I manually made changes as shown
below, but to no avail.

BEGIN lcd_core
PARAMETER INSTANCE = lcd_core_0
PARAMETER HW_VER = 1.00.a
PORT LCD_RW = lcd_core_0_LCD_RW
PORT LCD_RS = lcd_core_0_LCD_RS
PORT LCD_E = lcd_core_0_LCD_E
PORT LCD_D = lcd_core_0_LCD_D
PORT clk = sys_clk_s
PORT reset = sys_rst_s
# PORT din_ready = lcd_core_0_din_ready
# PORT din = lcd_core_0_din
# PORT busy = lcd_core_0_busy
PORT din_ready = FSL0_M_Write
PORT din = FSL0_M_Data (24 to 31)
PORT busy = FSL0_M_Full
END

- Lastly, I added the external ports from the LCD module to the UCF
file.

First, does this seem like the correct process to implement the
hardware peripheral? In the MPD file, do I need to uncomment the
IO_INTERFACE option for the LCD_x external outputs? How do I make the
connections to the FSL interface within Platform Studio?

When I try to generate the bitstream, I get the following error - I'm
sure I'm missing some type of port declaration, or am not performing
the right set of steps:
ERROR:MDT - INST:lcd_core_0 PORT:din_ready - C:\EDK_Test_LCD
\system.mhs line 187
- port is driven by a sourceless connector

Anyway, thanks so much for helping me throughout this process, and I
look forward to hearing back from you again!

Ray
.

Relevant Pages

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  • Re: Additional Hardware Module with Xilinx MicroBlaze Processor
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