Re: Prevent synthesis optimizations/simplifications in Xilinx-ISE

On Jul 25, 10:13 pm, "blak...@xxxxxxxxx" <blak...@xxxxxxxxx> wrote:
On Jul 25, 8:23 am, Gabor <ga...@xxxxxxxxxxx> wrote:



On Jul 25, 6:12 am, giorgos.puik...@xxxxxxxxx wrote:

Hello,

I want to implement a VHDL design in a Spartan3 device. Some
components of the design use cascaded inverters to produce one-shots
(short pulses). Upon synthesis, Xilinx-ISE simplifies the cascaded
inverters (e.g. if 6 inverters are cascaded it simply removes them
all). This alters the functionality of the design.

How can I configure ISE so that it does not perform such
simplifications (preferably per block, but if this is not possible for
the whole design)?

Thank you in advance guys!

Regards,
George

Unfortunately simple logic elements like inverters and gates will
always be mapped into LUT's regardless of any KEEP attributes on
the intermediate nets. You can however create such delay elements
by instantiating primitives like LUT's with the appropriate INIT
attributes to generate the functions you want. Look at the
Libraries guide to see your options for LUT instantiation.

I should add that this sort of design practice is generally frowned
upon in FPGA's, especially since there is a very wide variance in
delay due to process and temperature, and a possibly even wider
variance from build to build due to routing if you don't hand
place your delay elements. Usually you can use synchronous
techniques to create pulses and with a sufficiently fast clock
rate you can often ignore the discrete timing effects of the
synchronous pulse generator.

Regards,
Gabor- Hide quoted text -

- Show quoted text -

I know exactly what you need
use the attribute KEEP to prevent the wires between the inverters from
getting optimized away

(* keep = "true" *) wire [length-1:0] connect;

Additionally you can use LUT instantion primitives for anot gates as
shown

generate
genvar k;
for (k=0; k<length-1; k=k+1)
begin : not
LUT1 #(
.INIT(2'b01) // Specify LUT Contents
) LUT1k (
.O(connect[k+1]), // LUT general output
.I0(connect[k]) // LUT input
);
end
endgenerate

ENJOY!

Thank you very much guys! Your help is really appreciated.
Regards,
George
.

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