Re: Additional Hardware Module with Xilinx MicroBlaze Processor

On Jul 23, 3:26 pm, "Ray D." <ray.delvecc...@xxxxxxxxx> wrote:
On Jul 22, 2:34 am, "Göran Bilski" <goran.bil...@xxxxxxxxxx> wrote:



Hi,

Then it should be a direct match for the FSL interface.
If MicroBlaze executes a 'put' instruction , it will not write until the
FSL_M_Full flag is '0' and when it write it will set the FSL_M Write high
for one clock cycle.
MicroBlaze have plenty of options for the FSL instructions, you can get all
about them in the reference manual.

Göran

"Ray D." <ray.delvecc...@xxxxxxxxx> wrote in message

news:693f947e-929e-49f6-939d-d834e0048121@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
On Jul 21, 2:36 am, "Göran Bilski" <goran.bil...@xxxxxxxxxx> wrote:

Hi,

Depending a little on how your busy signals work, you might just hook up
your module to the FSL interface on MicroBlaze.
Your busy signal needs be high when it can't accept a new word even when
there is no attempt to write to the module.
MicroBlaze will also just do one cycle write so your module needs to
accept
a new word in one clock cycle when busy is low.

Connect:
din(7 downto 0) -> FSL0_M_Data(24 to 31)
din_ready -> FSL0_M_Write
busy -> FSL0_M_Full

You need to enable FSL Interfaces to MicroBlaze with the parameter
C_FSL_LINKS (set it to 1)
You can write to the fsl interface with the function putfslx, you can read
more about this function in the document "OS and Libraries Document
Collection".

Göran

"Ray D." <ray.delvecc...@xxxxxxxxx> wrote in message

news:276dce6d-c9ed-4937-95ea-e3c86ff3656a@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx

Hey all,

I have a Xilinx Spartan-3E starter board, and I'm implementing a
MicroBlaze processor on the FPGA. I would also like to use the LCD
which is on board, and I have already developed a hardware module that
takes care of initialization and printing to the LCD. The interface
is shown below:

entity LCD_top is
Port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;

din : in STD_LOGIC_VECTOR (7 downto 0);
din_ready : in STD_LOGIC;
busy : out STD_LOGIC;

LCD_D : out STD_LOGIC_VECTOR (11 downto 8);
LCD_E : out STD_LOGIC;
LCD_RS : out STD_LOGIC;
LCD_RW : out STD_LOGIC

);
end LCD_top;

I really would like to instantiate this module along with the
processor core. My question is this - how would I go about
interfacing this with the MicroBlaze processor internal to the FPGA?
What I would like to do is define a GPIO port on the processor to
connect to the din, din_ready and busy lines of the LCD module, but I
keep getting the following error:

ERROR:MDT - INST:LCD_data_status_10Bit PORT:GPIO_IO
CONNECTOR:LCD_data_status_10Bit_GPIO_IO - C:\EDK_Test_LCD
\system.mhs line 150
- connection is not connected to an external port!
MPD subproperties IOB_STATE=BUF|REG or THREE_STATE=TRUE require
that the port
be connected directly to an external port.

Is there any way to work around this? I realize I could just connect
the LCD to the GPIO directly and write software drivers, but I'm
trying to avoid that because I already have the hardware module in
place and working smoothly. It will also be nice to have this
separate module so that it does the work of printing to the LCD, and
the processor itself can stay busy with other more important jobs.

Also, is there an easier way to add another hardware module without
manually editing the generated VHDL files for the core? I'm not sure
if you can do that within Platform Studio.

Any advice would be much appreciated, thanks!

Ray

That is how the module works so I'll have to try some of these
options! The busy signal is set high the entire time data is being
written to the LCD. Originally I had a module "program.vhd" that
controlled the LCD module along with a keyboard module that we we had
in place for user input. Within program.vhd, I implement a state
machine and check if the busy signal is high before writing to the
LCD. If busy = 0, then I set din_ready high and set the 8-bits of
data. This is buffered within the LCD module and you only need to
hold din_ready for a single cycle to write to the LCD. The LCD is
connected over a 4-bit interface to the FPGA and this is taken care of
within the LCD module. When the writing operation begins busy is set
to '1' until complete.

Ray

OK - I'm new to using the EDK and am having trouble implementing this
with the FSL bus. I have a few questions:

1) When I create a custom peripheral, it generates an HDL wrapper - Do
I simply edit this wrapper by instantiating my LCD_top module as a
component within the top level design?

2) Should I check the box "Generate template driver files to help you
implement software interface", or will the provided functions to read
and write to the FSL bus suffice?

3) Do you know of any good tutorials on how to implement a custom
peripheral on the FSL bus? I've come across a few for adding
peripherals to the other buses, but most that I have found do not
follow through with how to edit the VHDL files and correctly add the
peripheral to the system in Platform Studio (they simply tell you go
to 'Create/Import Custom Peripheral').

Any help/input is appreciated, thanks!

Ray

Two more things -

1) the four output ports of the LCD module must be connected to the
external FPGA pins in order to drive the LCD. What is the best way to
go about doing this? Is this something that can be edited within
Platform Studio or do I need to manually edit VHDL/UCF files? I'm
assuming I will have to add the outputs to the interface shown below.

2) When I choose the master interface for the FSL bus, the ports are
defined as follows:

-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add or delete.
FSL_Clk : in std_logic;
FSL_Rst : in std_logic;
FSL_S_Clk : out std_logic;
FSL_S_Read : out std_logic;
FSL_S_Data : in std_logic_vector(0 to 31);
FSL_S_Control : in std_logic;
FSL_S_Exists : in std_logic;
FSL_M_Clk : out std_logic;
FSL_M_Write : out std_logic;
FSL_M_Data : out std_logic_vector(0 to 31);
FSL_M_Control : out std_logic;
FSL_M_Full : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------

You mention that my din(7 downto 0) port should be connected to the
FSL_M_Data port, but the former is an input while the latter is an
output. Am I missing something? I tried to define this as a slave
interface, but that also yields an error when I try to generate the
bitstream.

Thanks.
.

Relevant Pages

  • Re: Additional Hardware Module with Xilinx MicroBlaze Processor
    ... Then it should be a direct match for the FSL interface. ... MicroBlaze have plenty of options for the FSL instructions, ... Depending a little on how your busy signals work, ... I would also like to use the LCD ...
    (comp.arch.fpga)
  • Re: Additional Hardware Module with Xilinx MicroBlaze Processor
    ... Your busy signal needs be high when it can't accept a new word even ... You can write to the fsl interface with the function putfslx, ... I would also like to use the LCD ... What I would like to do is define a GPIO port on the processor to ...
    (comp.arch.fpga)
  • Re: Additional Hardware Module with Xilinx MicroBlaze Processor
    ... Your busy signal needs be high when it can't accept a new word even ... You can write to the fsl interface with the function putfslx, ... I would also like to use the LCD ... What I would like to do is define a GPIO port on the processor to ...
    (comp.arch.fpga)
  • Re: Additional Hardware Module with Xilinx MicroBlaze Processor
    ... Depending a little on how your busy signals work, ... MicroBlaze will also just do one cycle write so your module needs to accept ... You can write to the fsl interface with the function putfslx, ... I would also like to use the LCD ...
    (comp.arch.fpga)
  • Re: Additional Hardware Module with Xilinx MicroBlaze Processor
    ... Depending a little on how your busy signals work, ... MicroBlaze will also just do one cycle write so your module needs to accept ... You can write to the fsl interface with the function putfslx, ... What I would like to do is define a GPIO port on the processor to ...
    (comp.arch.fpga)