Re: Chipscope data port limitation to 256 bits
Thanks for your inputs guys, but the thing is that I get now from XST
the following error
NUmber of bounded IOBs 484 out of 248 195% (OVERMAPPED)
So it seems that the FPGA just allows me to have a a certain number if
input/output information and I cant really read out all the information
in the registers...
That error sounds to me to be about external IOs not about FPGA internal
So You do use 484 external Ports within Your toplevel file and do only
have something like 248 Pins available? Maybe you should consider
multiplexing Your IOs within some wrapper or fully connect Your design
to Your module under test.
That is not a chipscope limitation. That is a limitation caused by Your
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