Re: multicyle and false path in FPGA Design
- From: "HT-Lab" <hans64@xxxxxxxxxx>
- Date: Fri, 11 Jul 2008 09:15:12 +0100
<ekavirsrikanth@xxxxxxxxx> wrote in message
news:51facbfd-43fa-4247-810e-51c7d658ec5b@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
Hi All,
How to identify the Multi cycle path and the False path in the design.
do we need to identify after the Synthesis stage xilinx fpga tool it
self will recognize and through as warning or error.
If this is a medium/high budget project I would speak to the Fishtail
(http://www.fishtail-da.com/) guys. Their Focus product will automatically
find most(all?) MCP/FP in your design and output the result to a constraints
file. I believe both Precision/Synplicity are supported. This is a great
product but as I mentioned mostly for the big guys.
If you have to do this manually then start by looking at the most negative
slack path and simply plough through the code/schematics to see if that path
is false/multicycle or not. It is not going to be easy or quick especially
for false path. If you have access to a formal tool or PSL/SVA support for
your simulator then you might be able to write a property to check that, for
example, and enable pin on the output of a long combinatorial path FF is
always stable for more than 1 clockcycle.
Hans.
www.ht-lab.com
At what stage in the asic flow this multicycle path and False path are
identified. How to fix this Multi cycle path and false path in the
fpga flow
How it is going to effect the Timing Closure and the Slack of the
design.
regards
kil
.
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