Re: FIR in FPGA

On Thu, 29 May 2008 06:04:36 PDT, fazulu deen wrote:

Are you familiar with the concept of "clock enable"?
yes i do..I asked during implementation wat is max clock frequency can
i set for the example pointed out by me...

FIR filters can (in almost all applications) be pipelined
as deeply as necessary, so the upper limit on clock frequency
is much the same as you would get for any other logic in
the same technology. All that's needed is to enable all
the FIR's registers for one clock cycle on each sample
(i.e. at the appropriate sample rate). Not hard.

I asked...
Are you sure it [symmetric FIR structure]
needs more adders than an equivalent canonical
implementation? What leads you to believe that?

Have you ever seen the symmetric and non symmetric structure structure
before once u see u will also believe in it..

I know how to build an N-tap non-symmetric FIR using
N multipliers and N-1 adders. And I know how to build
a symmetric or antisymmetric N-tap FIR using ceil(N/2)
multipliers and N-1 adders (some are subtractors, if it's
antisymmetric). So I don't see why you think you need
extra adders in the symmetric/antisymmetric case. Do you
know some additional tricks that I don't?

Do you understand the concept of linearity? Can you think of
anything that might make your filter non-linear? (Clue:
my previous question about overflow). Do you trust your adder,
multiplier and register building blocks?
yes i do..critical path might make it non-linear....

My point is this: if it's truly linear, and it gives the
correct impulse response, then it's correct; no further
testing is needed. However, nonlinearity could easily
be introduced by...
- buggy multiplier or adder blocks
- arithmetic overflow
- improperly connected input bits that were not exercised
by the impulse test

if these are real problems of understanding, then please give us a
clue about what you already know and
what you find difficult.

my problems are mentioned as questions and few comments about the
currents progress to get the answers from the group..

I'm none the wiser.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@xxxxxxxxxxxxx
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
.

Relevant Pages
Loading