Re: Sequentially syncrhronous

On May 28, 11:24 am, Brian Philofsky
<brian.philofsky@xxxxxxxxxxxxxxxxxx> wrote:
KJ wrote:
On May 28, 6:50 am, "MikeWhy" <boat042-nos...@xxxxxxxxx> wrote:

This very well could be a timing issue but another possible cause of
this could be the writing of simulatable code but not synthesizable
code.  Looking at the code, I see the signals a and b in the sensitivity
list of the process which could cause the else statement to get
evaluated asynchronously in simulation however for synthesis, the
sensitivity list is likely ignored (generally with a warning) and thus
processed differently.  

Having 'a' and 'b' in the sensitivity list is not the problem. The
structure of the code is
process(...)
begin
if (rst = '1') then
...assignements here
elsif (clk'event and clk = '1') then
...assignements here
end if;
end process;

There are no assignments to anything outside of the if statement.
That if statement is of the form for flops with async presets/resets.
Having 'extra' signals in the sensitivity list will not result in any
difference between simulation and synthesis. If it does, then contact
the synthesis tool provider and submit a bug report.

KJ
I suggest removing the a and b signals from the
sensitivity list and see if the behavioral simulation still works.  My
guess is that may reveal your issue however if that does not, then I do
suggest looking more closely at the synthesis logs as well as timing
analysis to ensure it is not another synthesis mis-match issue or timing
issue.

In general, is it always this difficult and fraught with peril? I write
 >2000 lines/month in C++ with only minor misspelling mishaps. These 50 lines
have caused me more gray hairs than many whole systems.

Hardware design (even if written in a software like language such as
VHDL or Verilog) is not the same as software.  You can be well skilled
in the one discipline and at the same time be unskilled in the other.

It is all what you are used to.  I can not write C++ worth a lick so it
would likely take me a long time to write a program using it however I
feel I am very proficient with VHDL and Verilog.

Also, is there a way to tell XST to not treat reset as a clock? I haven't
fully read up on configuration, having spent way too much time on this
little time waster.

What makes you think that it is using reset as a clock?

I imagine you are referring to XST using a global buffer for the reset
signal.  In general this should not cause any issues and many times can
be the right thing to do but if you want to go to prevent that behavior,
tell XST you want an IBUF on the reset signal by adding the following
attribute:

attribute BUFFER_TYPE : string;
attribute BUFFER_TYPE of rst: signal is "IBUF";

This will force it to use a regular I/O instead of a global buffer.

Hope this helps and do not get too discouraged.  If you are just
learning, I could also suggest you try Verilog over VHDL.  I am not
trying to start the holy wars of languages but many do feel it is less
of a leap from C to Verilog than VHDL.  Again, I am not trying to start
a language debate so please leave do not let my statement start one.

--  Brian



Last, .... is this really worth pursuing? I've been programming for 25
years, and know that the greatest leassons come after the greatest pain.. But
there's also good pain, and just senseless injury. Is this not a suitable
first Zen parable to contemplate? I'm goaded forward by the belief that
there's a good lesson on synchronous systems lurking as the punchline.

The punchline might be static timing analysis.  Signals don't just
'happen' when you want them to, you need to guarantee by design that
they arrive at the proper time relative to the clock.

Kevin Jennings- Hide quoted text -

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