comp.arch.fpga

Thread Index

Re: error when 'generating simulation hdl files' in xilinx xps
- From: fatfpga@xxxxxxxxxxxxxx
Re: Need comparison table about Xilinx ISE WebPack 10.1i vs ISE Foundation 10.1i
- From: Roger
Re: cutoff frequency
- From: MikeWhy
Re: cutoff frequency
- From: John_H
Re: cutoff frequency
- From: Mike Treseler
Re: Can I make ISE 9.2 ngdbuild stop generating new PERIOD specs on PLL outputs?
- From: Barry
Re: cutoff frequency
- From: KJ
xilinx and jtag
- From: discussions
Re: cutoff frequency
- From: Frank Buss
Re: cutoff frequency
- From: fazulu deen
Re: cutoff frequency
- From: Frank Buss
Re: cutoff frequency
- From: Icky Thwacket
Re: cutoff frequency
- From: Icky Thwacket
Re: cutoff frequency
- From: fazulu deen
Re: cutoff frequency
- From: Jonathan Bromley
Re: cutoff frequency
- From: Icky Thwacket
Re: New Xilinx device package options for S3E & S3A
- From: Antti
cutoff frequency
- From: fazulu deen
cutoff frequency
- From: fazulu deen
Re: Xilinx Clock Doubler
- From: Symon
Re: (won't even attempt to try again .. .. ..)
- From: Ray Andraka
Re: (won't even attempt to try again .. .. ..)
- From: Ray Andraka
Re: DATA0 pin in Cyclone III device
- From: ghelbig
Re: Can I make ISE 9.2 ngdbuild stop generating new PERIOD specs on PLL outputs?
- From: Barry
Re: Xilinx Clock Doubler
- From: mk
Re: Are FPGAs headed toward a coarse granularity?
- From: Kolja Sulimma
Re: Can I make ISE 9.2 ngdbuild stop generating new PERIOD specs on PLL outputs?
- From: Kevin Neilson
Re: asic gate count
- From: Muzaffer Kal
Re: asic gate count
- From: Mike Lewis
Can I make ISE 9.2 ngdbuild stop generating new PERIOD specs on PLL outputs?
- From: Barry
DATA0 pin in Cyclone III device
- From: Hua
Re: delta sigma adc.....
- From: parekh . sh
Re: (won't even attempt to try again .. .. ..)
- From: Brian Davis
Re: Are FPGAs headed toward a coarse granularity?
- From: David Brown
dual port ramb16 problem
- From: Enes Erdin
Re: asic gate count
- From: backhus
Re: Xilinx Clock Doubler
- From: backhus
Re: (won't even attempt to try again .. .. ..)
- From: MikeWhy
Re: Xilinx LogicCore Direct Instantiation
- From: krw
Re: Xilinx Clock Doubler
- From: Symon
Re: Xilinx Clock Doubler
- From: Symon
Re: Xilinx Clock Doubler
- From: Grant Stockly
Re: Xilinx Clock Doubler
- From: Symon
Re: (won't even attempt to try again .. .. ..)
- From: Ray Andraka
Re: Problem writing quadrature decoder
- From: Mike Treseler
Re: (won't even attempt to try again .. .. ..)
- From: MikeWhy
Re: Xilinx Clock Doubler
- From: Grant Stockly
Re: Xilinx Clock Doubler
- From: Eric Smith
Re: using EXP connector of Spartan 3a board
- From: bish
Re: Are FPGAs headed toward a coarse granularity?
- From: Peter Alfke
Re: Xilinx Clock Doubler
- From: Peter Alfke
Re: Are FPGAs headed toward a coarse granularity?
- From: Kolja Sulimma
Re: FIR in FPGA
- From: Jonathan Bromley
Re: Are FPGAs headed toward a coarse granularity?
- From: David Brown
Re: FIR in FPGA
- From: fazulu deen
Re: FIR in FPGA
- From: Jonathan Bromley
Re: Are FPGAs headed toward a coarse granularity?
- From: Kolja Sulimma
Re: RGB video panel
- From: Brian Drummond
Re: error when 'generating simulation hdl files' in xilinx xps
- From: Brian Drummond
Re: Xilinx LogicCore Direct Instantiation
- From: Brian Drummond
Re: asic gate count
- From: Brian Drummond
FIR in FPGA
- From: fazulu deen
Re: Xilinx Clock Doubler
- From: Symon
Re: Xilinx Clock Doubler
- From: Grant Stockly
RGB video panel
- From: Ankit
Xilinx Clock Doubler
- From: Grant Stockly
Re: Ph.D Student
- From: Pablo
Re: Sequentially syncrhronous
- From: MikeWhy
Re: Virtex 2 with PLB_v34 and EDK 10.1
- From: Markus
Re: Sequentially syncrhronous
- From: MikeWhy
Re: HDL - simulation vs synthesis
- From: backhus
Re: Are FPGAs headed toward a coarse granularity?
- From: Jim Granville
Re: asic gate count
- From: Thomas Stanka
Are FPGAs headed toward a coarse granularity?
- From: rickman
Re: Sequentially syncrhronous
- From: rickman
Re: HDL - simulation vs synthesis
- From: jared . pierce
Re: Sequentially syncrhronous
- From: rickman
Re: Sequentially syncrhronous
- From: rickman
Re: Sequentially syncrhronous
- From: KJ
Re: Sequentially syncrhronous
- From: Jim Granville
Re: Sequentially syncrhronous
- From: Jim Granville
Re: Sequentially syncrhronous
- From: Jim Granville
Re: Xilinx LogicCore Direct Instantiation
- From: krw
Re: Sequentially syncrhronous
- From: MikeWhy
Re: Software instabilities with EDK 10.01 and PPC405?!??!!!
- From: Philipp Hachtmann
Re: Sequentially syncrhronous
- From: KJ
Re: FIFO verses RAMB
- From: John_H
Re: Sequentially syncrhronous
- From: Peter Alfke
FIFO verses RAMB
- From: Erik Anderson
Re: Sequentially syncrhronous
- From: MikeWhy
Re: HDL - simulation vs synthesis
- From: Mike Treseler
Re: asic gate count
- From: vijayant.rutgers@xxxxxxxxx
Re: HDL - simulation vs synthesis
- From: Jon Beniston
Re: Sequentially syncrhronous
- From: MikeWhy
HDL - simulation vs synthesis
- From: jared . pierce
Re: Sequentially syncrhronous
- From: KJ
Re: signal value at power up
- From: KJ
Re: Sequentially syncrhronous
- From: Brian Philofsky
Re: EDK 10.1 Map Error
- From: raghunandan85
Re: Sequentially syncrhronous
- From: rickman
Virtex 2 with PLB_v34 and EDK 10.1
- From: rmeiche
Re: Sequentially syncrhronous
- From: Mike Treseler
Re: Need comparison table about Xilinx ISE WebPack 10.1i vs ISE Foundation 10.1i
- From: John Adair
Re: Sequentially syncrhronous
- From: KJ
error when 'generating simulation hdl files' in xilinx xps
- From: fatfpga@xxxxxxxxxxxxxx
Sequentially syncrhronous
- From: MikeWhy
Re: impact / encrypted bitstream
- From: dajjou
JTAG + PROM error!
- From: jidan1
Re: Ph.D Student
- From: Pablo H
Re: XILINX core generator question
- From: Zorjak
Re: signal value at power up
- From: Thomas Stanka
Re: XILINX core generator question
- From: MM
Re: Ph.D Student
- From: Andreas Ehliar
Need comparison table about Xilinx ISE WebPack 10.1i vs ISE Foundation 10.1i
- From: Eka
Re: Mathstar plans to discontinue FPOA development
- From: Mike Treseler
Re: Downloading external data file to FPGA
- From: glen herrmannsfeldt
Re: 'Nother one bites the dust
- From: Jim Granville
Re: using EXP connector of Spartan 3a board
- From: Bryan
Re: 'Nother one bites the dust
- From: austin
'Nother one bites the dust
- From: austin
Re: Downloading external data file to FPGA
- From: Mike Treseler
Mathstar plans to discontinue FPOA development
- From: Jim Granville
Re: Video stream over bluetooth
- From: Narendra Sisodiya
Re: Downloading external data file to FPGA
- From: Fei Liu
Re: Xilinx LogicCore Direct Instantiation
- From: Rob Gaddi
Re: impact / encrypted bitstream
- From: dajjou
Re: Incremental compilation problem
- From: Hua
Re: XUPV2P and EDK 10.1
- From: Antony
Re: Video stream over bluetooth
- From: Mike Treseler
Re: XILINX core generator question
- From: Zorjak
Re: impact / encrypted bitstream
- From: morphiend
Re: EDK 10.1 Map Error
- From: morphiend
Re: Xilinx IO drive level constrain
- From: Symon
HWICAP initialization
- From: fmostafa
Re: FIR filter o/p width
- From: Jonathan Bromley
FIR filter o/p width
- From: fazulu deen
Re: Xilinx IO drive level constrain
- From: kislo
Ph.D Student
- From: Pablo
Re: XILINX core generator question
- From: raghunandan85
Re: EDK 10.1 Map Error
- From: raghunandan85
Re: Downloading external data file to FPGA
- From: Moazzam
Re: impact / encrypted bitstream
- From: dajjou
Re: Downloading external data file to FPGA
- From: Moazzam
Re: Downloading external data file to FPGA
- From: Moazzam
Re: Downloading external data file to FPGA
- From: Moazzam
impact / encrypted bitstream
- From: dajjou
Re: signal value at power up
- From: Kolja Sulimma
Re: signal value at power up
- From: Goli
Re: using EXP connector of Spartan 3a board
- From: MikeWhy
Re: signal value at power up
- From: rickman
Re: How to update a row and a column at the same clock cycle?
- From: rickman
Re: signal value at power up
- From: martstev
Re: signal value at power up
- From: Thomas Stanka
signal value at power up
- From: martstev
Re: Xilinx IO drive level constrain
- From: Symon
Xilinx IO drive level constrain
- From: kislo
Re: Incremental compilation problem
- From: gquan
Re: Downloading external data file to FPGA
- From: sijo2000
Re: Downloading external data file to FPGA
- From: Enes Erdin
Re: How to update a row and a column at the same clock cycle?
- From: Nicolas Matringe
Re: Downloading external data file to FPGA
- From: Florian
Re: FPGA Programing file
- From: David Spencer
Re: Downloading external data file to FPGA
- From: Enes Erdin
Re: Xilinx XCL woes
- From: PFC
Downloading external data file to FPGA
- From: Florian
Incremental compilation problem
- From: Hua
Xilinx XCL woes
- From: PFC
How to update a row and a column at the same clock cycle?
- From: R. Hofman
Re: EDK 10.1 Map Error
- From: morphiend
XILINX core generator question
- From: Zorjak
Re: Problem when for program and data memory use SDRAM
- From: axalay
Re: timing constraint is impossible to meet
- From: Gabor
Problem when for program and data memory use SDRAM
- From: axalay
Re: 1250gbps input on virtex-5
- From: Kolja Sulimma
using EXP connector of Spartan 3a board
- From: bish
Re: Software instabilities with EDK 10.01 and PPC405?!??!!!
- From: Philipp Hachtmann
Re: FPGA Programing file
- From: Uwe Bonnes
Re: FPGA Programing file
- From: fazulu deen
Re: FPGA Programing file
- From: rickman
Re: FPGA Programing file
- From: cherin99
Re: Stratix IV Announced
- From: rickman
Re: New Xilinx device package options for S3E & S3A
- From: rickman
New Xilinx device package options for S3E & S3A
- From: M.Randelzhofer
Re: Video stream over bluetooth
- From: Narendra Sisodiya
Re: Stratix IV Announced
- From: turkey_bird
EDK 10.1 Map Error
- From: raghunandan85
XST 3.0 Xess Audio to Ethernet
- From: Scutum612
Why this RLOC cannot be used two times?
- From: fl
Xilinx LogicCore Direct Instantiation
- From: krw
Re: Stratix IV Announced
- From: turkey_bird
Re: Software instabilities with EDK 10.01 and PPC405?!??!!!
- From: John McCaskill
Re: Software instabilities with EDK 10.01 and PPC405?!??!!!
- From: Philipp Hachtmann
Microblaze Cache and FSL problem
- From: ratemonotonic
Re: asic gate count
- From: glen herrmannsfeldt
Video stream over bluetooth
- From: Narendra Sisodiya
FPGA Programing file
- From: cherin99
Re: globals
- From: Symon
Re: it doesn't work if increase a little traffic for DMA read.
- From: water9580@xxxxxxxxx
incremental compilation
- From: Hua
Re: Software instabilities with EDK 10.01 and PPC405?!??!!!
- From: Alan Nishioka
Re: 1250gbps input on virtex-5
- From: Peter Alfke
Xilinx EDK inferred dual port BRAM unconnected clkb
- From: mozilla
Re: it doesn't work if increase a little traffic for DMA read.
- From: Rob Gaddi
Re: Simple PRNG problem -> clk not recognised as input
- From: Rob Gaddi
Re: XILINX Ethernet MAC (URGENT...)
- From: morphiend
Re: asic gate count
- From: Jon Beniston
Re: asic gate count
- From: Mike Lewis
it doesn't work if increase a little traffic for DMA read.
- From: water9580@xxxxxxxxx
HWICAP and BRAM
- From: fmostafa
Re: Simple PRNG problem -> clk not recognised as input
- From: Dan Arik
Re: Simple PRNG problem -> clk not recognised as input
- From: Dan Arik
Simple PRNG problem -> clk not recognised as input
- From: Dan Arik
Avalon interconnect fabric : arbiter
- From: Charles Wagner
Software instabilities with EDK 10.01 and PPC405?!??!!!
- From: Philipp Hachtmann
Re: URGENT :problem using Ethernet MAC ip core...
- From: Symon
Re: globals
- From: Symon
Re: 1250gbps input on virtex-5
- From: Symon
Re: timing constraint is impossible to meet
- From: Martin Thompson
Re: 1250gbps input on virtex-5
- From: Kolja Sulimma
Re: asic gate count
- From: glen herrmannsfeldt
URGENT :problem using Ethernet MAC ip core...
- From: vikram
globals
- From: uche
Re: 1250gbps input on virtex-5
- From: Peter Alfke
Re: asic gate count
- From: Mike Lewis
asic gate count
- From: vijayant.rutgers@xxxxxxxxx
Re: Yay! We're done with the quadrature encoder!
- From: MikeWhy
Re: timing constraint is impossible to meet
- From: Jonathan Bromley
Re: timing constraint is impossible to meet
- From: Rob Gaddi
Re: 1250gbps input on virtex-5
- From: austin
ISE 10.1 FPGA Editor
- From: jimmydunstan
Xilinx XCF Flash ROMs - does a datasheet for erase and programming exist?
- From: Fred
1250gbps input on virtex-5
- From: Kolja Sulimma
Re: Stratix IV Announced
- From: Antti
Re: problem with microblaze connected ip core
- From: taco
problem with microblaze connected ip core
- From: taco
Re: timing constraint is impossible to meet
- From: HT-Lab
Re: Every newbie's favorite project: the Quadrature Rotary Encoder revisited
- From: MikeWhy
Re: timing constraint is impossible to meet
- From: PatC
Re: timing constraint is impossible to meet
- From: vasu
Re: XILINX Ethernet MAC (URGENT...)
- From: vikram
Re: bizarre state machine behavior
- From: Jim Granville
Re: synthesis...
- From: fazulu deen
Re: synthesis...
- From: Andreas Ehliar
Re: bizarre state machine behavior
- From: KJ
Re: Every newbie's favorite project: the Quadrature Rotary Encoder revisited
- From: Eric Smith
Re: Every newbie's favorite project: the Quadrature Rotary Encoder revisited
- From: Frank Buss
Re: Every newbie's favorite project: the Quadrature Rotary Encoder revisited
- From: Eric Smith
Re: RS232 Interface
- From: Jürgen Böhm
Re: RS232 Interface
- From: Jonathan Bromley
Re: Every newbie's favorite project: the Quadrature Rotary Encoder revisited
- From: Jim Granville
Re: Stratix IV Announced
- From: Jim Granville
Re: Every newbie's favorite project: the Quadrature Rotary Encoder revisited
- From: Jon Elson
Re: Every newbie's favorite project: the Quadrature Rotary Encoder revisited
- From: Mike Treseler
Re: bizarre state machine behavior
- From: Jon Elson
Re: bizarre state machine behavior
- From: Jon Elson
Re: Every newbie's favorite project: the Quadrature Rotary Encoder revisited
- From: austin
Every newbie's favorite project: the Quadrature Rotary Encoder revisited
- From: MikeWhy
Re: RS232 Interface
- From: Rob Gaddi
RS232 Interface
- From: Dan Arik
Re: synthesis...
- From: fazulu deen
Re: synthesis...
- From: Andreas Ehliar
Re: XILINX Ethernet MAC (URGENT...)
- From: morphiend
Re: timing constraint is impossible to meet
- From: Symon
Re: Stratix IV Announced
- From: Antti
Re: timing constraint is impossible to meet
- From: Brian Drummond
Re: timing constraint is impossible to meet
- From: wzab
Re: timing constraint is impossible to meet
- From: Symon
Re: Stratix IV Announced
- From: Jon Beniston
timing constraint is impossible to meet
- From: Wojciech Zabolotny
Re: Problem with Scheduler in Xilkernel.
- From: Jespr
Re: Stratix IV Announced
- From: Fredrik
Re: 2-bit Pseudo Random Number Generator
- From: backhus
Re: Stratix IV Announced
- From: Peter Alfke
Re: XILINX Ethernet MAC (URGENT...)
- From: vikram
Re: Stratix IV Announced
- From: Kim Enkovaara
Re: bizarre state machine behavior
- From: Jeff Cunningham
Re: 2-bit Pseudo Random Number Generator
- From: Jeff Cunningham
Re: bizarre state machine behavior
- From: Symon
Re: Instantiating an lpm dcfifo in Verilog
- From: jjlindula@xxxxxxxxxxx
Re: bizarre state machine behavior
- From: Jim Granville
Re: bizarre state machine behavior
- From: Mike Treseler
Re: bizarre state machine behavior
- From: Jon Elson
Re: my Spartan-4 wishlist
- From: PFC
Re: HELP: a Funny asynchronous input design
- From: Aiken
Instantiating an lpm dcfifo in Verilog
- From: jjlindula@xxxxxxxxxxx
Re: Stratix IV Announced
- From: Mike Treseler
Re: my Spartan-4 wishlist
- From: Uwe Bonnes
Re: HELP: a Funny asynchronous input design
- From: Peter Alfke
Re: I cannot find how to map a "record type" in my ucf file.
- From: Kevin Neilson
Re: Stratix IV Announced
- From: austin
Re: synthesis...
- From: John_H
Re: HELP: a Funny asynchronous input design
- From: Gabor
Re: HELP: a Funny asynchronous input design
- From: Aiken
Re: synthesis...
- From: Kolja Sulimma
Re: synthesis...
- From: Andreas Ehliar
Re: Problem with Scheduler in Xilkernel.
- From: Guy Eschemann
Re: 2-bit Pseudo Random Number Generator
- From: Symon
Re: my Spartan-4 wishlist
- From: PFC
Re: Stratix IV Announced
- From: John Adair
Re: I cannot find how to map a "record type" in my ucf file.
- From: Pablo
Re: SKEW greater than Time period of CLK
- From: Thomas Stanka
Re: Problem with Scheduler in Xilkernel.
- From: Jespr
synthesis...
- From: fazulu deen
V4 - VTRX & AVCCAUXRX
- From: akshat
Re: Problem with conversions.vhd
- From: rickman
Re: HELP: a Funny asynchronous input design
- From: Peter Alfke
Re: synthesis...
- From: Andreas Ehliar
Re: bizarre state machine behavior
- From: Symon
Re: bizarre state machine behavior
- From: Jeff Cunningham
Re: Incorporating FPGAs on PCBs
- From: PFC
Re: bizarre state machine behavior
- From: Rob Gaddi
bizarre state machine behavior
- From: Jon Elson
Re: 2-bit Pseudo Random Number Generator
- From: Jeff Cunningham
Re: Stratix IV Announced
- From: Jim Granville
HELP: a Funny asynchronous input design
- From: Aiken
Announcing Virtex 57!
- From: austin
Re: Resetting FPGA Without watch dog timer
- From: ratemonotonic
Re: I cannot find how to map a "record type" in my ucf file.
- From: KJ
Re: Resetting FPGA Without watch dog timer
- From: Jim Granville
Re: I cannot find how to map a "record type" in my ucf file.
- From: Mike Treseler
Stratix IV Announced
- From: John Adair
I cannot find how to map a "record type" in my ucf file.
- From: Pablo
Re: Resetting FPGA Without watch dog timer
- From: Peter Alfke
Re: 2-bit Pseudo Random Number Generator
- From: Rob Gaddi
Re: SKEW greater than Time period of CLK
- From: ghelbig
Re: frame format virtex 5
- From: austin
Re: Resetting FPGA Without watch dog timer
- From: austin
Re: frame format virtex 5
- From: bamboutcha9999
Re: 2-bit Pseudo Random Number Generator
- From: Arlet Ottens
Re: 2-bit Pseudo Random Number Generator
- From: Kolja Sulimma
Re: 2-bit Pseudo Random Number Generator
- From: Clemens
Re: 2-bit Pseudo Random Number Generator
- From: Jonathan Bromley
Re: Problem with Scheduler in Xilkernel.
- From: morphiend
Re: XILINX Ethernet MAC (URGENT...)
- From: morphiend
2-bit Pseudo Random Number Generator
- From: Clemens
Re: System configuration for Xilinx ISE 10.1 - Virtex 5 LX110t or bigger FPGA
- From: morphiend
Re: Cyclone 3 margins: none at all at 3.3v
- From: Dolphin
Re: Problem with conversions.vhd
- From: Brian Drummond
Re: Camera link interface
- From: Crhonos04
Re: Camera link interface
- From: Crhonos04
Re: Resetting FPGA Without watch dog timer
- From: ratemonotonic
Re: Resetting FPGA Without watch dog timer
- From: ratemonotonic
Re: difference between 8.2i and 9.2i with respect to Microblaze Core
- From: G�ran Bilski
Problem with Scheduler in Xilkernel.
- From: Jespr
Re: difference between 8.2i and 9.2i with respect to Microblaze Core
- From: karthick
SKEW greater than Time period of CLK
- From: kris2552
Re: System configuration for Xilinx ISE 10.1 - Virtex 5 LX110t or bigger FPGA
- From: Moazzam
XILINX Ethernet MAC (URGENT...)
- From: vikram
Re: ANNC: FPGA Design Software Webcast
- From: Alex
Re: Incorporating FPGAs on PCBs
- From: rickman
Re: Problem with conversions.vhd
- From: rickman
Re: Problem with conversions.vhd
- From: Jonathan Bromley
Re: Problem with conversions.vhd
- From: Brian Drummond
XSA-50 implementation
- From: uche
Re: Problem with conversions.vhd
- From: Brian Drummond
Re: Problem with conversions.vhd
- From: rickman
Problem with conversions.vhd
- From: rickman
Re: FPGA art
- From: checo
Xilinx ISE simulator
- From: rickman
Re: FPGA art
- From: Enes Erdin
FPGA art
- From: checo
Re: Incorporating FPGAs on PCBs
- From: Enes Erdin
Re: Camera link interface
- From: Rob
Re: Resetting FPGA Without watch dog timer
- From: Symon
Re: Incorporating FPGAs on PCBs
- From: glen herrmannsfeldt
Re: Resetting FPGA Without watch dog timer
- From: glen herrmannsfeldt
Re: Vref IO problems with DDR SDRAM memory controller on a Virtex 4 LX25, ML401 board
- From: Brian Drummond
Re: difference between 8.2i and 9.2i with respect to Microblaze Core
- From: wicky
Re: PCI to SATA of industrial class ( -40 - 85 )
- From: wicky
Re: Cyclone 3 margins: none at all at 3.3v
- From: austin
Re: Camera link interface
- From: Brad Smallridge
System configuration for Xilinx ISE 10.1 - Virtex 5 LX110t or bigger FPGA
- From: explore
Re: Resetting FPGA Without watch dog timer
- From: Peter Alfke
Re: Incorporating FPGAs on PCBs
- From: ghelbig
Re: Incorporating FPGAs on PCBs
- From: O. Olson
Re: frame format virtex 5
- From: austin
Re: Incorporating FPGAs on PCBs
- From: Enes Erdin
frame format virtex 5
- From: dajjou
Re: Incorporating FPGAs on PCBs
- From: Rob Gaddi
Re: What could be the problem?
- From: Muzaffer Kal
Re: Resetting FPGA Without watch dog timer
- From: austin
Re: Incorporating FPGAs on PCBs
- From: O. Olson
agen Xilinx di Indonesia
- From: bmw318ie96
Re: What could be the problem?
- From: David Spencer
Resetting FPGA Without watch dog timer
- From: ratemonotonic
Re: Cyclone 3 margins: none at all at 3.3v
- From: austin
Re: Incorporating FPGAs on PCBs
- From: Enes Erdin
Re: Incorporating FPGAs on PCBs
- From: O. Olson
Re: Incorporating FPGAs on PCBs
- From: Enes Erdin
Re: Incorporating FPGAs on PCBs
- From: O. Olson
Vref IO problems with DDR SDRAM memory controller on a Virtex 4 LX25, ML401 board
- From: mspiegels
Re: What could be the problem?
- From: Brian Drummond
Re: Incorporating FPGAs on PCBs
- From: Brian Drummond
Re: FPGA imp
- From: Brian Drummond
Re: Incorporating FPGAs on PCBs
- From: Enes Erdin
Re: What could be the problem?
- From: Pablo
Re: Incorporating FPGAs on PCBs
- From: O. Olson
Re: Incorporating FPGAs on PCBs
- From: Kolja Sulimma
Re: What could be the problem?
- From: backhus
Re: Length between blocks in FPGA
- From: backhus
What could be the problem?
- From: Pablo
Incorporating FPGAs on PCBs
- From: O. Olson
Re: Camera link interface
- From: JPiqueras . M
Length between blocks in FPGA
- From: Enes Erdin
Re: distributed RAM / BRAM
- From: Symon
Re: Cyclone 3 on chip termination
- From: Karl
Re: Cyclone 3 on chip termination
- From: Karl
distributed RAM / BRAM
- From: bamboutcha9999
LwBT port for microblaze
- From: Narendra Sisodiya
difference between 8.2i and 9.2i with respect to Microblaze Core
- From: karthick
Re: Open source Core generators?
- From: Guenter Dannoritzer
Re: Cyclone 3 on chip termination
- From: Rob
Re: Camera link interface
- From: Rob
Re: How do I get Xilinx EDK to load a 'custom' XBD file?
- From: Bryan
Re: xilinx spi core question (microblaze)
- From: radarman
Re: Programming XCR3064xl - voltage at output stuck at 0
- From: xcr3064xl
Re: Functional Simulation of Virtex-4 Block Memory
- From: Ray Andraka
Re: Camera link interface
- From: Brad Smallridge
Re: question about high speed serial links with clock forwarding in Virtex5 FPGAs
- From: austin
Re: How do I get Xilinx EDK to load a 'custom' XBD file?
- From: ghelbig
Re: Camera link interface
- From: wicky
PCI to SATA of industrial class ( -40 - 85 )
- From: wicky
Re: Cyclone 3 on chip termination
- From: austin
Altera Cyclone 3 external clamping diode
- From: Dolphin
Re: Camera link interface
- From: mamu
question about high speed serial links with clock forwarding in Virtex5 FPGAs
- From: magne . munkejord
Re: Camera link interface
- From: Enes Erdin
Re: Camera link interface
- From: Enes Erdin
Re: FPGA imp
- From: fazulu deen
Camera link interface
- From: Crhonos04
Re: FPGA imp
- From: Kolja Sulimma
Re: Yay! We're done with the quadrature encoder!
- From: Symon
Re: xilinx beginner modelsim question
- From: Zorjak
Cyclone 3 on chip termination
- From: Dolphin
Re: FPGA imp
- From: fazulu deen
xilinx spi core question (microblaze)
- From: taco
Re: FPGA imp
- From: Kolja Sulimma
FPGA imp
- From: fazulu deen
How do I get Xilinx EDK to load a 'custom' XBD file?
- From: ghelbig
Re: xsa-50 issues
- From: Jecel
Re: Programming XCR3064xl - voltage at output stuck at 0
- From: Jim Granville
Re: Programming XCR3064xl - voltage at output stuck at 0
- From: xcr3064xl
Re: Yay! We're done with the quadrature encoder!
- From: Jon Elson
Re: demo board under 500usd
- From: ghelbig
Re: How to input an analog signal to FPGA board for processing?
- From: Vagant
Re: xilinx beginner modelsim question
- From: Dave
Re: xilinx beginner modelsim question
- From: Barry
problem in using ICAP
- From: fmostafa
demo board under 500usd
- From: kclo4
xilinx beginner modelsim question
- From: Zorjak
Re: Yay! We're done with the quadrature encoder!
- From: Jim Granville
About the user defined instruction in APU
- From: louis
Re: Problem writing quadrature decoder
- From: Jim Granville
Yay! We're done with the quadrature encoder!
- From: John_H
Re: Problem writing quadrature decoder
- From: Peter Alfke
Re: Problem writing quadrature decoder
- From: Peter Alfke
Re: power supply noise margin
- From: austin
Re: Problem writing quadrature decoder
- From: Jim Granville
Re: Problem writing quadrature decoder
- From: John_H
Re: Problem writing quadrature decoder
- From: Jim Granville
Re: Problem writing quadrature decoder
- From: glen herrmannsfeldt
power supply noise margin
- From: kislo
Re: 5 V oscillator output to GCLK
- From: glen herrmannsfeldt
Re: Problem writing quadrature decoder
- From: Peter Alfke
Re: Programming XCR3064xl - voltage at output stuck at 0
- From: xcr3064xl
Re: Programming XCR3064xl - voltage at output stuck at 0
- From: xcr3064xl
Need help on ASIC/ASSP FGPA-based prototyping and verification survey
- From: John Blyler
Re: Problem writing quadrature decoder
- From: Jim Granville
Re: Virtex XCV1000E-6FG860C
- From: Peter Alfke
www.e-bayshoe.com wholesale jordan air max 90 95 ltd
- From: ebayshoe2
Re: Problem writing quadrature decoder
- From: John_H
Re: Problem with PlanAhead on Partial Reconfiguration on ML403 (Virtex 4)
- From: G_Abgrall
Re: 5 V oscillator output to GCLK
- From: Kolja Sulimma
Re: Problem writing quadrature decoder
- From: Jim Granville
Re: Problem writing quadrature decoder
- From: John_H
xsa-50 issues
- From: uche
Re: Problem writing quadrature decoder
- From: Jim Granville
Re: Problem writing quadrature decoder
- From: John_H
Re: Problem writing quadrature decoder
- From: Jim Granville
Re: Problem writing quadrature decoder
- From: Jim Granville
Re: How to input an analog signal to FPGA board for processing?
- From: Andy Peters
Re: Programming XCR3064xl - voltage at output stuck at 0
- From: Jim Granville
Re: Problem writing quadrature decoder
- From: John_H
Re: Problem writing quadrature decoder
- From: Jim Granville
Re: Problem writing quadrature decoder
- From: Jim Granville
Re: Problem writing quadrature decoder
- From: Jim Granville
Re: Problem writing quadrature decoder
- From: Jim Granville
Programming XCR3064xl - voltage at output stuck at 0
- From: xcr3064xl
Re: Problem writing quadrature decoder
- From: Peter Alfke
Re: Problem writing quadrature decoder
- From: John_H
Re: Problem writing quadrature decoder
- From: Jim Granville
Re: How to input an analog signal to FPGA board for processing?
- From: MM
Re: How to input an analog signal to FPGA board for processing?
- From: Vagant
Re: how to set trigger in ChipScopePro for this
- From: Pratap
Re: value of the weak pull up resistor on IOBs of Virtex5
- From: austin
Re: Is Virtex 4 supported by Jbits ?
- From: austin
Re: RLC package parasitics
- From: austin
Re: Anyway to secure a Xilinx NGC file ?
- From: austin
Re: Getting started with VHDL and Verilog
- From: Matthew Hicks
Re: Problem writing quadrature decoder
- From: John_H
Re: How to input an analog signal to FPGA board for processing?
- From: Frank Buss
Re: How to input an analog signal to FPGA board for processing?
- From: Vagant
Re: value of the weak pull up resistor on IOBs of Virtex5
- From: Frank Buss
value of the weak pull up resistor on IOBs of Virtex5
- From: Goli
Is Virtex 4 supported by Jbits ?
- From: swissiyoussef
Re: How to input an analog signal to FPGA board for processing?
- From: kclo4
sdio controller in fpga
- From: Alan Nishioka
How to input an analog signal to FPGA board for processing?
- From: Vagant
Re: Problem writing quadrature decoder
- From: Jim Granville
Re: Problem writing quadrature decoder
- From: John_H
Re: Problem writing quadrature decoder
- From: Eric Smith
has anyone made PLB_DDR work with 1Gb DRAM chips?
- From: Jeff Cunningham
Re: RLC package parasitics
- From: David Spencer
Re: Problem writing quadrature decoder
- From: Jim Granville
RLC package parasitics
- From: kislo
Re: Problem writing quadrature decoder
- From: Frank Buss
Re: Problem writing quadrature decoder
- From: Peter Alfke
Re: Problem writing quadrature decoder
- From: Jim Granville
Re: Problem writing quadrature decoder
- From: Peter Alfke
Re: Problem writing quadrature decoder
- From: nospam
Re: how to set trigger in ChipScopePro for this
- From: Brian Drummond
Re: Problem writing quadrature decoder
- From: Eric Smith
Re: Problem writing quadrature decoder
- From: Jim Granville
Re: Problem writing quadrature decoder
- From: John_H
Re: 5 V oscillator output to GCLK
- From: Peter Alfke
Re: Problem writing quadrature decoder
- From: Peter Alfke
Re: how to set trigger in ChipScopePro for this
- From: Joseph Samson
Re: how to set trigger in ChipScopePro for this
- From: Marty Ryba
Re: 5 V oscillator output to GCLK
- From: KJ
how to set trigger in ChipScopePro for this
- From: Pratap
Re: 5 V oscillator output to GCLK
- From: KJ
Re: Anyway to secure a Xilinx NGC file ?
- From: John McCaskill
Re: Anyway to secure a Xilinx NGC file ?
- From: Muzaffer Kal
Xilinx ML507 evaluation board (V5FXT70)?
- From: TSIuser
Re: getting samples from an RF board onto the system
- From: Arlet Ottens
getting samples from an RF board onto the system
- From: vits
Re: ISE 9.2 - how do I extract component/slice placements for locking down a design?
- From: Fred
Re: Problem writing quadrature decoder
- From: Jim Granville
Re: 5 V oscillator output to GCLK
- From: Jim Granville
Re: Anyway to secure a Xilinx NGC file ?
- From: fpganut
Re: Problem writing quadrature decoder
- From: glen herrmannsfeldt
udp receive problem under nios
- From: bjzhangwn@xxxxxxxxx
Re: 5 V oscillator output to GCLK
- From: pdudley1@xxxxxxxxxxx
Re: 5 V oscillator output to GCLK
- From: Peter Alfke
Re: 5 V oscillator output to GCLK
- From: Jim Granville
Protect yourself against Operation Sudden Fall
- From: Neal . Jaradat
Re: 5 V oscillator output to GCLK
- From: Peter Alfke
Re: 5 V oscillator output to GCLK
- From: Jim Granville
Re: 5 V oscillator output to GCLK
- From: Peter Alfke
Re: 5 V oscillator output to GCLK
- From: KJ
Re: 5 V oscillator output to GCLK
- From: KJ
Re: 5 V oscillator output to GCLK
- From: KJ
Re: 5 V oscillator output to GCLK
- From: Peter Alfke
Re: ISE 9.2 - how do I extract component/slice placements for locking down a design?
- From: SoyAnarchisto
Re: 5 V oscillator output to GCLK
- From: Jon Elson
Re: 5 V oscillator output to GCLK
- From: David Spencer
Re: Anyway to secure a Xilinx NGC file ?
- From: SoyAnarchisto
Re: 5 V oscillator output to GCLK
- From: Jim Granville
Re: Virtex XCV1000E-6FG860C
- From: austin
Re: Virtex XCV1000E-6FG860C
- From: jon
Re: Spartan 3 Mapping Problem
- From: Rob Gaddi
Re: Anyway to secure a Xilinx NGC file ?
- From: austin
Re: Chirp generator / CORDIC algo ?
- From: Duane Clark
Re: ISE 9.2 - how do I extract component/slice placements for locking down a design?
- From: Kevin Neilson
Re: 5 V oscillator output to GCLK
- From: John_H
ISE 9.2 - how do I extract component/slice placements for locking down a design?
- From: Fred
Re: 5 V oscillator output to GCLK
- From: KJ
Re: 5 V oscillator output to GCLK
- From: David Spencer
Re: Vritex2PRO: LVDCI for inputs?
- From: austin
Re: Quartus 7.2 and PCI Express
- From: axalay
Re: Quartus 7.2 and PCI Express
- From: axalay
Re: 5 V oscillator output to GCLK
- From: Kolja Sulimma
Re: Quartus 7.2 and PCI Express
- From: Górski Adam
Re: Xilinx Platform USB Cable II
- From: Clemens
Re: 5 V oscillator output to GCLK
- From: Brian Drummond
Re: Xilinx Platform USB Cable II
- From: sky465nm
Vritex2PRO: LVDCI for inputs?
- From: Goli
Re: Xilinx Platform USB Cable II
- From: Clemens
Xilinx Platform USB Cable II
- From: Clemens
5 V oscillator output to GCLK
- From: maverick
Anyway to secure a Xilinx NGC file ?
- From: fpganut
Re: Spartan 3 Mapping Problem
- From: Marvin
Re: Spartan 3 Mapping Problem
- From: John_H
Re: Spartan 3 Mapping Problem
- From: Rob Gaddi
Re: Spartan 3 Mapping Problem
- From: John_H
Spartan 3 Mapping Problem
- From: Rob Gaddi
Re: Virtex XCV1000E-6FG860C
- From: BobW
Re: Virtex XCV1000E-6FG860C
- From: austin
Virtex XCV1000E-6FG860C
- From: jon
Re: Quartus 7.2 and PCI Express
- From: axalay
Re: EDK for spartan2?
- From: ghelbig
Re: Quartus 7.2 and PCI Express
- From: ghelbig
ML300 evaluation board broken?
- From: PG
Re: Quartus 7.2 and PCI Express
- From: axalay
Re: Quartus 7.2 and PCI Express
- From: Górski Adam
Re: Quartus 7.2 and PCI Express
- From: axalay
Re: Argh! Need help debugging Xilinx .xsvf Player (XAPP058) RESOLVED
- From: MM
Re: ps2 mouse protocol
- From: whygee
Re: Quartus 7.2 and PCI Express
- From: Górski Adam
Quartus 7.2 and PCI Express
- From: axalay
Re: Chirp generator / CORDIC algo ?
- From: XSterna
Re: EDK for spartan2?
- From: Markus
Dual rank DDR2 memory for Xilinx ML410 board
- From: louis
EDK for spartan2?
- From: taco
Re: PCI Express Switch
- From: Philip Joe
Re: ps2 mouse protocol
- From: Matthias Alles
Re: Problem writing quadrature decoder
- From: Jim Granville
Re: Chirp generator / CORDIC algo ?
- From: Ray Andraka
Re: ANNC: FPGA Design Software Webcast
- From: John_H
Re: Problem writing quadrature decoder
- From: Peter Alfke
Re: Argh! Need help debugging Xilinx .xsvf Player (XAPP058) RESOLVED
- From: Bob
Re: Argh! Need help debugging Xilinx .xsvf Player (XAPP058) RESOLVED
- From: MM
Re: Argh! Need help debugging Xilinx .xsvf Player (XAPP058) RESOLVED
- From: Bob
Re: FPGA dev kit with 4-8 Cyclones or Spartans
- From: Gavin Scott
Re: Problem writing quadrature decoder
- From: Jim Granville
ps2 mouse protocol
- From: Thorsten Kiefer
Re: DSP48 Inference Template for XST
- From: Kevin Neilson
Does anyone have sdio protocol experience?
- From: Alan Nishioka
Re: Getting started with VHDL and Verilog
- From: Guenter Dannoritzer
Re: FPGA dev kit with 4-8 Cyclones or Spartans
- From: John Adair
Re: FPGA dev kit with 4-8 Cyclones or Spartans
- From: Gavin Scott
Re: FPGA dev kit with 4-8 Cyclones or Spartans
- From: climber . tim
DSP48 Inference Template for XST
- From: Kevin Neilson
NGC / EDIF Viewer
- From: Kevin Neilson
Re: FPGA dev kit with 4-8 Cyclones or Spartans
- From: Gavin Scott
Re: FPGA dev kit with 4-8 Cyclones or Spartans
- From: Nathan Bialke
Re: FPGA dev kit with 4-8 Cyclones or Spartans
- From: austin
FPGA dev kit with 4-8 Cyclones or Spartans
- From: climber . tim
Re: Call VHDL module from Verilog
- From: Mike Treseler
Re: Call VHDL module from Verilog
- From: egadget1
Re: Xilinx ISE 10 in CentOS not showing in application menu list
- From: Nicolas Hervé
Call VHDL module from Verilog
- From: egadget1
Re: Getting started with VHDL and Verilog
- From: Mike Treseler
Re: Getting started with VHDL and Verilog
- From: jraj . thakkar
Re: Getting started with VHDL and Verilog
- From: jraj . thakkar
Re: Aldec Active-HDL 7.3 sp1 [stimulators]
- From: Patrick Dubois
Re: BRAM initialization / bitstream configuration
- From: bamboutcha9999
Re: Xilinx xilfatfs and systemACE speed issue
- From: UETIAN
Re: Getting started with VHDL and Verilog
- From: austin
Getting started with VHDL and Verilog
- From: jraj . thakkar
Re: Argh! Need help debugging Xilinx .xsvf Player (XAPP058)
- From: Bob
Re: Argh! Need help debugging Xilinx .xsvf Player (XAPP058)
- From: Bob
Re: warning from ISE 9.2
- From: Dave
Re: warning from ISE 9.2
- From: Thorsten Kiefer
Re: Argh! Need help debugging Xilinx .xsvf Player (XAPP058)
- From: MM
warning from ISE 9.2
- From: Thorsten Kiefer
Re: BRAM initialization / bitstream configuration
- From: austin
Re: Getting started with VHDL and Verilog
- From: Andreas Ehliar
BRAM initialization / bitstream configuration
- From: bamboutcha9999
Re: How program PROM from msc file
- From: Arlet Ottens
How program PROM from msc file
- From: zuzaila
Using Sysgen v8.2
- From: Partha
Xilinx ISE 10 in CentOS not showing in application menu list
- From: Simon
Re: Aldec Active-HDL 7.3 sp1 [stimulators]
- From: 0xdeadbeef
Looking for FPGA/CPLD skills to develop prototype
- From: cjt101
Re: Argh! Need help debugging Xilinx .xsvf Player (XAPP058)
- From: Bob
Re: Argh! Need help debugging Xilinx .xsvf Player (XAPP058)
- From: Bob
Re: Problem writing quadrature decoder
- From: Peter Alfke
Re: Argh! Need help debugging Xilinx .xsvf Player (XAPP058)
- From: Martin Darwin
Re: NIOS II CFI interface
- From: ghelbig
Re: Argh! Need help debugging Xilinx .xsvf Player (XAPP058)
- From: MM
Re: Argh! Need help debugging Xilinx .xsvf Player (XAPP058)
- From: Bob
Re: Argh! Need help debugging Xilinx .xsvf Player (XAPP058)
- From: Andreas Hölscher
Re: EDK9.2i simulation problems.
- From: G�ran Bilski
Re: FPGA Processor for Signal Processing ?
- From: Andreas Ehliar
EDK9.2i simulation problems.
- From: chrisdekoh
Re: Old FPGA question
- From: whygee
Re: Using SRL16 with reset
- From: Nico Coesel
need recommendation for PCB fab & BGA assembly vendor, I'm in SF bay area
- From: fpganut
Re: Argh! Need help debugging Xilinx .xsvf Player (XAPP058)
- From: Bob
Re: Using SRL16 with reset
- From: austin
Re: FPGA Processor for Signal Processing ?
- From: Brian Drummond
Re: FPGA Processor for Signal Processing ?
- From: morphiend
Re: Old FPGA question
- From: Nicolas Matringe
Re: Old FPGA question
- From: whygee
Re: asic gate count
- From: vijayant.rutgers@xxxxxxxxx
Re: PLB Master Example
- From: raghunandan85
Re: Using SRL16
- From: Alain
Re: Using SRL16
- From: John_H
FPGA Processor for Signal Processing ?
- From: HansWernerMarschke
Re: Using SRL16
- From: Sean Durkin
Re: Using SRL16
- From: jprovidenza
Re: Using SRL16
- From: austin
Re: Using SRL16
- From: Mike Treseler
Using SRL16
- From: Partha
Re: Aldec Active-HDL 7.3 sp1 [stimulators]
- From: Mike Treseler
Aldec Active-HDL 7.3 sp1 [stimulators]
- From: 0xdeadbeef
Re: Argh! Need help debugging Xilinx .xsvf Player (XAPP058)
- From: MM
Re: Argh! Need help debugging Xilinx .xsvf Player (XAPP058)
- From: Bob
Re: Old FPGA question
- From: John Adair
Re: Argh! Need help debugging Xilinx .xsvf Player (XAPP058)
- From: Antti
Re: Argh! Need help debugging Xilinx .xsvf Player (XAPP058)
- From: MM
Re: xilinx remote platform flash program
- From: MM
Re: Virtex4 Output Pins during Configuration
- From: austin
Re: Quartus v7.x fitting bug
- From: Mike Treseler
Re: Virtex4 Output Pins during Configuration
- From: Nemesis
Re: Virtex4 Output Pins during Configuration
- From: austin
Re: Quartus v7.x fitting bug
- From: KJ
xilinx remote platform flash program
- From: bishopg12
Re: Quartus v7.x fitting bug
- From: Mike Treseler
Re: Argh! Need help debugging Xilinx .xsvf Player (XAPP058)
- From: Bob
Quartus v7.x fitting bug
- From: ian . barnes
Re: Chirp generator / CORDIC algo ?
- From: XSterna
Re: XCF02S not seen in the JTAG chain
- From: AugustoEinsfeldt
Re: Argh! Need help debugging Xilinx .xsvf Player (XAPP058)
- From: Gabor
Re: asic gate count
- From: RCIngham
Re: PCI Express Switch
- From: Kolja Sulimma
Virtex4 Output Pins during Configuration
- From: Nemesis
Re: asic gate count
- From: Thomas Stanka
Re: NIOS II CFI interface
- From: bjzhangwn@xxxxxxxxx
Re: Functional Simulation of Virtex-4 Block Memory
- From: Mike Treseler
Re: Argh! Need help debugging Xilinx .xsvf Player (XAPP058)
- From: Bob
Re: Functional Simulation of Virtex-4 Block Memory
- From: Jeff Cunningham
Re: Functional Simulation of Virtex-4 Block Memory
- From: Duane Clark
Re: Argh! Need help debugging Xilinx .xsvf Player (XAPP058)
- From: MM
Re: Functional Simulation of Virtex-4 Block Memory
- From: Jeff Cunningham
Argh! Need help debugging Xilinx .xsvf Player (XAPP058)
- From: Bob
Re: FLASH vs SRAM (was Re: Old FPGA question)
- From: whygee
Re: sobel in vhdl
- From: Jim Lewis
Re: FLASH vs SRAM (was Re: Old FPGA question)
- From: Duane Clark
Re: Old FPGA question
- From: Duane Clark
Re: sobel in vhdl
- From: Kevin Neilson
Re: Old FPGA question
- From: whygee
FLASH vs SRAM (was Re: Old FPGA question)
- From: whygee
Re: Old FPGA question
- From: cs_posting
Re: Virtex4 DCM doesn't work unless freezing cold
- From: msn444
Re: Old FPGA question
- From: Duane Clark
Re: Old FPGA question
- From: Duane Clark
Re: Chirp generator / CORDIC algo ?
- From: MM
Re: asic gate count
- From: vijayant.rutgers@xxxxxxxxx
Old FPGA question
- From: whygee
Re: Functional Simulation of Virtex-4 Block Memory
- From: Duane Clark
Re: Functional Simulation of Virtex-4 Block Memory
- From: Peter Alfke
Re: Functional Simulation of Virtex-4 Block Memory
- From: Duane Clark
Re: NIOS II CFI interface
- From: ghelbig
Re: Functional Simulation of Virtex-4 Block Memory
- From: Mike Treseler
Re: Functional Simulation of Virtex-4 Block Memory
- From: charles . elias
Re: ARM Cortex for Altera available
- From: Antti
Re: ARM Cortex for Altera available
- From: Jon Beniston
Re: Chirp generator / CORDIC algo ?
- From: XSterna
ARM Cortex for Altera available
- From: Antti
NIOS II CFI interface
- From: bjzhangwn@xxxxxxxxx
Re: asic gate count
- From: Mike Treseler
Re: asic gate count
- From: Vijayant
Re: Functional Simulation of Virtex-4 Block Memory
- From: Duane Clark
Re: how can i recover my unencrypted bitstream starting from encrypted one and knowing the KEY
- From: Eric Smith
Re: how to optimize this comparator for better synthesis result?
- From: water9580@xxxxxxxxx
Re: Functional Simulation of Virtex-4 Block Memory
- From: Brad Smallridge