comp.arch.fpga

• Date Index

---

• co-sim for handel C with modelsim vs pure modelsim VHDL simulation, chrisdekoh
  • Re: co-sim for handel C with modelsim vs pure modelsim VHDL simulation, Mike Treseler
• PCI Express Switch, shakith . fernando
• Virtex4 DCM doesn't work unless freezing cold, msn444
  • Re: Virtex4 DCM doesn't work unless freezing cold, Symon
  • Re: Virtex4 DCM doesn't work unless freezing cold, MM
  • Re: Virtex4 DCM doesn't work unless freezing cold, austin
    • Re: Virtex4 DCM doesn't work unless freezing cold, austin
• what's the difference between .rba & .rbb files ?, bamboutcha9999
  • Re: what's the difference between .rba & .rbb files ?, swissiyoussef
• XUPV2P and EDK 10.1, Antony
• how to optimize this comparator for better synthesis result?, water9580@xxxxxxxxx
  • Re: how to optimize this comparator for better synthesis result?, Tommy Thorn
  • Re: how to optimize this comparator for better synthesis result?, backhus
    • Re: how to optimize this comparator for better synthesis result?, Andy
  • <Possible follow-ups>
  • Re: how to optimize this comparator for better synthesis result?, Kolja Sulimma
• I use a ftp tool test my V5-based PCIE ethernet NIC controller., water9580@xxxxxxxxx
• XCF02S not seen in the JTAG chain, AugustoEinsfeldt
  • Re: XCF02S not seen in the JTAG chain, austin
    • Re: XCF02S not seen in the JTAG chain, AugustoEinsfeldt
      • Re: XCF02S not seen in the JTAG chain, austin
• Hand-editing xilinx.sys, Dave
• PPC + APU + FSL + Xilkernel Problem, u_stadler@xxxxxxxx
• Functional Simulation of Virtex-4 Block Memory, charles . elias
  • Re: Functional Simulation of Virtex-4 Block Memory, Duane Clark
  • Re: Functional Simulation of Virtex-4 Block Memory, Brad Smallridge
    • Re: Functional Simulation of Virtex-4 Block Memory, charles . elias
      • Re: Functional Simulation of Virtex-4 Block Memory, Duane Clark
• floating point and logarithm in vhdl+xilinx, digi . megabyte
  • Re: floating point and logarithm in vhdl+xilinx, HT-Lab
• Chirp generator / CORDIC algo ?, XSterna
  • Re: Chirp generator / CORDIC algo ?, Duane Clark
    • Re: Chirp generator / CORDIC algo ?, XSterna
  • Re: Chirp generator / CORDIC algo ?, Kevin Neilson
    • Re: Chirp generator / CORDIC algo ?, Kevin Neilson
• Virtex4 PPC405 - FPU problem, FreeRTOS.org
• INTERNATIONAL WORKSHOP ON OPTICAL SUPERCOMPUTING (OSC'08): Deadline extension, optical supercomputing
• parallel port using XSA-50, uche
• Problem with PlanAhead on Partial Reconfiguration on ML403 (Virtex 4), G_Abgrall
  • Re: Problem with PlanAhead on Partial Reconfiguration on ML403 (Virtex 4), G_Abgrall
• Could someone tell me NIOS II/MB performance on this benchmark?, Tommy Thorn
  • Re: Could someone tell me NIOS II/MB performance on this benchmark?, Göran Bilski
    • Re: Could someone tell me NIOS II/MB performance on this benchmark?, Göran Bilski
      • Re: Could someone tell me NIOS II/MB performance on this benchmark?, Tommy Thorn
      • Re: Could someone tell me NIOS II/MB performance on this benchmark?, Tommy Thorn
      • Re: Could someone tell me NIOS II/MB performance on this benchmark?, Göran Bilski
• Debounce in Verilog?, eromlignod
  • Re: Debounce in Verilog?, Jeff Cunningham
  • Re: Debounce in Verilog?, Thomas Stanka
  • Re: Debounce in Verilog?, Peter Alfke
  • Re: Debounce in Verilog?, John_H
• understanding xilinx silicon revisions (does ES come before CES4, etc.), Jeff Cunningham
  • Re: understanding xilinx silicon revisions (does ES come before CES4, etc.), MM
    • Re: understanding xilinx silicon revisions (does ES come before CES4, etc.), austin
  • Re: understanding xilinx silicon revisions (does ES come before CES4, etc.), austin
  • Re: understanding xilinx silicon revisions (does ES come before CES4, etc.), austin
• Darnaw1 Schematics, John Adair
• How to embed time and date in Xilinx FPGA?, freeagent . 20 . oracle
  • Re: How to embed time and date in Xilinx FPGA?, Symon
  • Re: How to embed time and date in Xilinx FPGA?, Phil Hays
• what's next?, Fei Liu
• Nano transistor breakthrough?, sky465nm
  • Re: Nano transistor breakthrough?, Jon Elson
• Quatech SPP 100 PCMCIA to Parallel Adapter for FPGA Board for Sale, Hendra
  • Re: Quatech SPP 100 PCMCIA to Parallel Adapter for FPGA Board for Sale, Hendra
• how can i recover my unencrypted bitstream starting from encrypted one and knowing the KEY, swissiyoussef
  • Re: how can i recover my unencrypted bitstream starting from encrypted one and knowing the KEY, austin
    • Re: how can i recover my unencrypted bitstream starting from encrypted one and knowing the KEY, swissiyoussef
      • Re: how can i recover my unencrypted bitstream starting from encrypted one and knowing the KEY, austin
      • Re: how can i recover my unencrypted bitstream starting from encrypted one and knowing the KEY, Symon
      • Re: how can i recover my unencrypted bitstream starting from encrypted one and knowing the KEY, austin
      • Re: how can i recover my unencrypted bitstream starting from encrypted one and knowing the KEY, Gavin Scott
      • Re: how can i recover my unencrypted bitstream starting from encrypted one and knowing the KEY, mowa
      • Re: how can i recover my unencrypted bitstream starting from encrypted one and knowing the KEY, austin
      • Re: how can i recover my unencrypted bitstream starting from encrypted one and knowing the KEY, Antti
      • Re: how can i recover my unencrypted bitstream starting from encrypted one and knowing the KEY, austin
      • Re: how can i recover my unencrypted bitstream starting from encrypted one and knowing the KEY, bamboutcha9999
      • Re: how can i recover my unencrypted bitstream starting from encrypted one and knowing the KEY, Tonda
      • Re: how can i recover my unencrypted bitstream starting from encrypted one and knowing the KEY, austin
      • Re: how can i recover my unencrypted bitstream starting from encrypted one and knowing the KEY, austin
• CRC algorithm, swissiyoussef
  • Re: CRC algorithm, Alan Nishioka
    • Re: CRC algorithm, swissiyoussef
    • Re: CRC algorithm, bommels
      • Re: CRC algorithm, swissiyoussef
• Virtex-4 inrush power-on current, MM
  • Re: Virtex-4 inrush power-on current, austin
    • Re: Virtex-4 inrush power-on current, KJ
      • Re: Virtex-4 inrush power-on current, BobW
      • Re: Virtex-4 inrush power-on current, KJ
      • Re: Virtex-4 inrush power-on current, austin
      • Re: Virtex-4 inrush power-on current, Rob
      • Re: Virtex-4 inrush power-on current, Peter Alfke
      • Re: Virtex-4 inrush power-on current, Peter Alfke
      • Re: Virtex-4 inrush power-on current, Rob
      • Re: Virtex-4 power-on current, austin
      • Re: Virtex-4 power-on current, MM
      • Re: Virtex-4 power-on current, austin
      • Re: Virtex-4 power-on current, MM
• How to arrange these SRL16 in a straight column, fl
  • Re: How to arrange these SRL16 in a straight column, Duane Clark
  • Re: How to arrange these SRL16 in a straight column, John_H
• Spartan3 "commercial" temperature range, dalai lamah
  • Re: Spartan3 "commercial" temperature range, Peter Alfke
    • Re: Spartan3 "commercial" temperature range, dalai lamah
  • Re: Spartan3 "commercial" temperature range, austin
    • Re: Spartan3 "commercial" temperature range, dalai lamah
      • Re: Spartan3 "commercial" temperature range, austin
• Timing closure problem --- how to make the QII fitter smarter, Hua
  • Re: Timing closure problem --- how to make the QII fitter smarter, ALuPin@xxxxxx
  • Re: Timing closure problem --- how to make the QII fitter smarter, Ed McGettigan
• PLB Master Example, raghunandan85
  • Re: PLB Master Example, Andy
    • Re: PLB Master Example, raghunandan85
• V5, EMAC simulation problem, when 4 EMACs are used together (ISE 10.1, ModelSim 6.3d), vboykov
• noob question, Thorsten Kiefer
  • Re: noob question, tarmopalm
  • Re: noob question, Symon
  • Re: noob question, KJ
  • Re: noob question, Philip Potter
  • Re: noob question, Brian Drummond
• delta sigma adc....., krunal
  • Re: delta sigma adc....., Symon
    • Re: -. . ..- ... --. .-. --- ..- --- .--., austin
      • Re: -. . ..- ... --. .-. --- ..- --- .--., Symon
      • Re: -. . ..- ... --. .-. --- ..- --- .--., austin
      • Re: -. . ..- ... --. .-. --- ..- --- .--., Symon
      • Re: -. . ..- ... --. .-. --- ..- --- .--., austin
      • Re: -. . ..- ... --. .-. --- ..- --- .--., Symon
      • Aldiss Lamps, etc., austin
      • Re: -. . ..- ... --. .-. --- ..- --- .--., none
      • Re: -. . ..- ... --. .-. ..- --- .--., austin
      • Re: -. . .-- ... --. .-. --- ..- .--., John_H
      • Re: (won't even attempt to try again .. .. ..), austin
• ATF750 for Proteus, Julio Espada
  • Re: ATF750 for Proteus, ghelbig
  • Re: ATF750 for Proteus, -jg
    • Re: ATF750 for Proteus, Julio Espada
• ACTEL FPGA static timing analysis, Shyam Sundar
• HydraXC + EDK, u_stadler@xxxxxxxx
  • Re: HydraXC + EDK, Antti
    • Re: HydraXC + EDK, u_stadler@xxxxxxxx
      • Re: HydraXC + EDK, Antti
      • Re: HydraXC + EDK, u_stadler@xxxxxxxx
      • Re: HydraXC + EDK, Antti
• video stream transfer via UART and Bluetooth in FPGA, Narendra Sisodiya
  • Re: video stream transfer via UART and Bluetooth in FPGA, Antti
    • Re: video stream transfer via UART and Bluetooth in FPGA, Narendra Sisodiya
      • Re: video stream transfer via UART and Bluetooth in FPGA, Antti
      • Re: video stream transfer via UART and Bluetooth in FPGA, Narendra Sisodiya
• will there be any problem with diffrent version of sysgen & EDK, Narendra Sisodiya
  • Re: will there be any problem with diffrent version of sysgen & EDK, ghelbig
    • Re: will there be any problem with diffrent version of sysgen & EDK, Narendra Sisodiya
      • Re: will there be any problem with diffrent version of sysgen & EDK, Narendra Sisodiya
      • Re: will there be any problem with diffrent version of sysgen & EDK, ghelbig
• superscalar processor design, Peter Glar
• FPGA comeback, RealInfo
  • Re: FPGA comeback, Symon
    • Re: FPGA comeback, oen_br
    • Message not available
      • Message not available
      • Re: FPGA comeback, RealInfo
      • Re: FPGA comeback, John_H
  • Re: FPGA comeback, austin
    • Re: FPGA comeback, H. Peter Anvin
• Verilog state machines, latches, syntax and a bet!, ee_ether
  • Re: Verilog state machines, latches, syntax and a bet!, Andreas Ehliar
  • Re: Verilog state machines, latches, syntax and a bet!, KJ
  • Re: Verilog state machines, latches, syntax and a bet!, Muzaffer Kal
    • Re: Verilog state machines, latches, syntax and a bet!, Muzaffer Kal
      • Re: Verilog state machines, latches, syntax and a bet!, Dave
      • Re: Verilog state machines, latches, syntax and a bet!, Muzaffer Kal
      • Re: Verilog state machines, latches, syntax and a bet!, KJ
  • Re: Verilog state machines, latches, syntax and a bet!, Eric Crabill
  • Re: Verilog state machines, latches, syntax and a bet!, Kevin Neilson
• 10.1 EDK - How can I create a user library in SDK?, andrew . nesterov
• the order in which some switches are turned on, laura
  • Re: the order in which some switches are turned on, backhus
  • Re: the order in which some switches are turned on, jkljljklk
  • Re: the order in which some switches are turned on, glen herrmannsfeldt
    • Re: the order in which some switches are turned on, Gabor
• Can somebody help about Period Timing Constraints, songrise
  • Re: Can somebody help about Period Timing Constraints, Symon
• FPGA Verilog state machine lock up, NN
  • Re: FPGA Verilog state machine lock up, Mike Treseler
• Xilinx is cancelling the Virtex-E XCV1000E-FG860, Alan Nishioka
  • Re: Xilinx is cancelling the Virtex-E XCV1000E-FG860, austin
    • Re: Xilinx is cancelling the Virtex-E XCV1000E-FG860, Alan Nishioka
      • Re: Xilinx is cancelling the Virtex-E XCV1000E-FG860, austin
      • Re: Xilinx is cancelling the Virtex-E XCV1000E-FG860, dalai lamah
      • Re: Xilinx is cancelling the Virtex-E XCV1000E-FG860, Uwe Bonnes
  • Re: Xilinx is cancelling the Virtex-E XCV1000E-FG860, Symon
    • Re: Xilinx is cancelling the Virtex-E XCV1000E-FG860, Alan Nishioka
      • Re: Xilinx is cancelling the Virtex-E XCV1000E-FG860, Symon
      • Re: Xilinx is cancelling the Virtex-E XCV1000E-FG860, Peter Alfke
  • Re: Xilinx is cancelling the Virtex-E XCV1000E-FG860, Peter Alfke
    • Re: Xilinx is cancelling the Virtex-E XCV1000E-FG860, Antti
  • Re: Xilinx is cancelling the Virtex-E XCV1000E-FG860, MH
    • Re: Xilinx is cancelling the Virtex-E XCV1000E-FG860, Alan Nishioka
• Need a few Xilinx Spartan FPGAs, Jon Elson
• Altera Cyc II config problems, bob elkind
• Newbie: Testbench question, jjlindula@xxxxxxxxxxx
  • Re: Newbie: Testbench question, jjlindula@xxxxxxxxxxx
    • Re: Newbie: Testbench question, RCIngham
  • Re: Newbie: Testbench question, HT-Lab
    • Re: Newbie: Testbench question, jjlindula@xxxxxxxxxxx
      • Re: Newbie: Testbench question, Nial Stewart
      • Re: Newbie: Testbench question, Stef
      • Re: Newbie: Testbench question, Philip Potter
      • Re: Newbie: Testbench question, jjlindula@xxxxxxxxxxx
• Turning off the DLL to run DDR2 at very low frequency, adubinsky457
  • Re: Turning off the DLL to run DDR2 at very low frequency, Kevin Neilson
    • Re: Turning off the DLL to run DDR2 at very low frequency, adubinsky457
      • Re: Turning off the DLL to run DDR2 at very low frequency, Kevin Neilson
  • Re: Turning off the DLL to run DDR2 at very low frequency, mng
  • Re: Turning off the DLL to run DDR2 at very low frequency, John Adair
• opb_intc + PowerPC, axalay
  • Re: opb_intc + PowerPC, Brian Drummond
    • Re: opb_intc + PowerPC, axalay
      • Re: opb_intc + PowerPC, Brian Drummond
• not inferred RAM, on QII, LC
  • Re: not inferred RAM, on QII, ALuPin@xxxxxx
    • Re: not inferred RAM, on QII, LC
    • Re: not inferred RAM, on QII, LC
  • Re: not inferred RAM, on QII, KJ
    • Re: not inferred RAM, on QII, LC
      • Re: not inferred RAM, on QII, Mike Treseler
      • Re: not inferred RAM, on QII, LC
• DCM configuration in Virtex-4 FPGA, mspiegels
  • Re: DCM configuration in Virtex-4 FPGA, MM
    • Re: DCM configuration in Virtex-4 FPGA, austin
      • Re: DCM configuration in Virtex-4 FPGA, mspiegels
      • Re: DCM configuration in Virtex-4 FPGA, MM
• Celoxica RC1000, Tim Pope
  • Re: Celoxica RC1000, HT-Lab
    • Re: Celoxica RC1000, Tim Pope
• OPB_MDM functionality, Pablo
• XmdStub fails when connecting via JTAG., Pablo
• Problem writing quadrature decoder, Michael
  • Re: Problem writing quadrature decoder, Mike Treseler
    • Re: Problem writing quadrature decoder, Michael
      • Re: Problem writing quadrature decoder, Mike Treseler
  • Re: Problem writing quadrature decoder, Frank Buss
    • Re: Problem writing quadrature decoder, Michael
      • Re: Problem writing quadrature decoder, -jg
      • Re: Problem writing quadrature decoder, Michael
      • Re: Problem writing quadrature decoder, Peter Alfke
      • Re: Problem writing quadrature decoder, Michael
      • Re: Problem writing quadrature decoder, Michael
      • Re: Problem writing quadrature decoder, John_H
      • Re: Problem writing quadrature decoder, bcuzeau
      • Re: Problem writing quadrature decoder, Michael
      • Re: Problem writing quadrature decoder, John_H
      • Re: Problem writing quadrature decoder, John_H
      • Re: Problem writing quadrature decoder, michael
      • Re: Problem writing quadrature decoder, Brian Drummond
      • Re: Problem writing quadrature decoder, -jg
      • Re: Problem writing quadrature decoder, glen herrmannsfeldt
      • Re: Problem writing quadrature decoder, Peter Alfke
  • Re: Problem writing quadrature decoder, Peter Alfke
    • Re: Problem writing quadrature decoder, Michael
      • Re: Problem writing quadrature decoder, Peter Alfke
      • Re: Problem writing quadrature decoder, Peter Alfke
      • Re: Problem writing quadrature decoder, Michael
      • Re: Problem writing quadrature decoder, Peter Alfke
      • Re: Problem writing quadrature decoder, -jg
      • Re: Problem writing quadrature decoder, Peter Alfke
      • Re: Problem writing quadrature decoder, -jg
      • Re: Problem writing quadrature decoder, glen herrmannsfeldt
      • Re: Problem writing quadrature decoder, Peter Alfke
      • Re: Problem writing quadrature decoder, -jg
      • Re: Problem writing quadrature decoder, Peter Alfke
      • Re: Problem writing quadrature decoder, -jg
      • Re: Problem writing quadrature decoder, Peter Alfke
      • Re: Problem writing quadrature decoder, -jg
      • Re: Problem writing quadrature decoder, Peter Alfke
      • Re: Problem writing quadrature decoder, none
      • Re: Problem writing quadrature decoder, Jim Granville
• synchronous reset problems on FPGA, chrisdekoh
  • Re: synchronous reset problems on FPGA, Mike Treseler
    • Re: synchronous reset problems on FPGA, chrisdekoh
      • Re: synchronous reset problems on FPGA, Peter Alfke
      • Re: synchronous reset problems on FPGA, chrisdekoh
      • Re: synchronous reset problems on FPGA, Peter Alfke
      • Re: synchronous reset problems on FPGA, chrisdekoh
      • Re: synchronous reset problems on FPGA, Lars
      • Re: synchronous reset problems on FPGA, Andy Peters
      • Re: synchronous reset problems on FPGA, Nial Stewart
      • Re: synchronous reset problems on FPGA, Mike Treseler
  • Re: synchronous reset problems on FPGA, HT-Lab
  • Re: synchronous reset problems on FPGA, KJ
• how we can prove that really the AES 256 is used to crypt the Bitstream in virtex 5, dajjou
• Very simple VHDL problem, Michael
  • Re: Very simple VHDL problem, Frank Buss
    • Re: Very simple VHDL problem, Michael
      • Re: Very simple VHDL problem, michael
      • Re: Very simple VHDL problem, Frank Buss
      • Re: Very simple VHDL problem, Michael
      • Re: Very simple VHDL problem, Brian Drummond
    • Re: Very simple VHDL problem, glen herrmannsfeldt
  • Re: Very simple VHDL problem, Nicolas Matringe
    • Re: Very simple VHDL problem, Michael
      • Re: Very simple VHDL problem, Symon
      • Re: Very simple VHDL problem, Nicolas Matringe
      • Re: Very simple VHDL problem, Kevin Neilson
      • Re: Very simple VHDL problem, KJ
      • Re: Very simple VHDL problem, HT-Lab
      • Re: Very simple VHDL problem, Kevin Neilson
      • Re: Very simple VHDL problem, Mike Treseler
      • Re: Very simple VHDL problem, Andy
• Synthesis Comparison, Moikel
  • Re: Synthesis Comparison, Mike Treseler
    • Re: Synthesis Comparison, Kolja Sulimma
      • Re: Synthesis Comparison, KJ
  • Re: Synthesis Comparison, KJ
• How to instantiate macro in verilog, Haile Yu (Harry)
  • Re: How to instantiate macro in verilog, Jim Wu
  • Re: How to instantiate macro in verilog, Kevin Neilson
    • Re: How to instantiate macro in verilog, Moazzam
      • Re: How to instantiate macro in verilog, Kevin Neilson
      • Re: How to instantiate macro in verilog, Moazzam
• Xilinx DDR2 Interface, ben
  • Re: Xilinx DDR2 Interface, Jim Wu
    • Re: Xilinx DDR2 Interface, ben
      • Re: Xilinx DDR2 Interface, Mike Harrison
    • Re: Xilinx DDR2 Interface, Kevin Neilson
      • Re: Xilinx DDR2 Interface, Gabor
      • Re: Xilinx DDR2 Interface, ben
• Has anyone dealt with Avnet? or NuHorizons when trying to purchase Xilinx stuff, Raban
  • Re: Has anyone dealt with Avnet? or NuHorizons when trying to purchase Xilinx stuff, Mike Treseler
  • Re: Has anyone dealt with Avnet? or NuHorizons when trying to purchase Xilinx stuff, Ken Ryan
  • Re: Has anyone dealt with Avnet? or NuHorizons when trying to purchase Xilinx stuff, John Adair
    • Re: Has anyone dealt with Avnet? or NuHorizons when trying to purchase Xilinx stuff, Georg Acher
• Chipscope is Failing, oshea
• New to FPGA : Timing Closure, ratemonotonic
  • Re: New to FPGA : Timing Closure, Jon Beniston
  • Re: New to FPGA : Timing Closure, KJ
• Chip photos of old FPGAs, Andreas Ehliar
  • Re: Chip photos of old FPGAs, Andreas Ehliar
• Re: Survey: FPGA PCB layout, Mike Treseler
  • <Possible follow-ups>
  • Re: Survey: FPGA PCB layout, Symon
    • Re: Survey: FPGA PCB layout, Andy
      • Re: Survey: FPGA PCB layout, Symon
  • Re: Survey: FPGA PCB layout, Symon
• XST design frequency setting, robquigley
  • Re: XST design frequency setting, Mike Treseler
  • Re: XST design frequency setting, HT-Lab
  • Re: XST design frequency setting, Brian Davis
• DMA in PLB custom core (XilinxV4), myx2
• Help, router can't rout all connections (XILINX), Mark
  • Re: Help, router can't rout all connections (XILINX), Symon
    • Re: Help, router can't rout all connections (XILINX), Mark
    • Re: Help, router can't rout all connections (XILINX), Brian Drummond
  • Re: Help, router can't rout all connections (XILINX), HT-Lab
    • Re: Help, router can't rout all connections (XILINX), Mark
    • Re: Help, router can't rout all connections (XILINX), Mark
• how do I test signals in a testbench that are 1 or 2 levels down in the UUT?, Dan K
  • Re: how do I test signals in a testbench that are 1 or 2 levels down in the UUT?, Mike Treseler
  • Re: how do I test signals in a testbench that are 1 or 2 levels down in the UUT?, RCIngham
  • Re: how do I test signals in a testbench that are 1 or 2 levels down in the UUT?, HT-Lab
    • Re: how do I test signals in a testbench that are 1 or 2 levels down in the UUT?, Duane Clark
      • Re: how do I test signals in a testbench that are 1 or 2 levels down in the UUT?, HT-Lab
  • Re: how do I test signals in a testbench that are 1 or 2 levels down in the UUT?, KJ
  • Re: how do I test signals in a testbench that are 1 or 2 levels down in the UUT?, Andy
• ICAP_VIRTEX4 primitive, rha_x
  • Re: ICAP_VIRTEX4 primitive, Erik Anderson
• chipscope pro , lower level signals not visible, ni
  • Re: chipscope pro , lower level signals not visible, Patrick Dubois
• 91c111 drivers for NIOSII without ucosII/lwip stack, bjzhangwn@xxxxxxxxx
• Virtex 4 DCM problem, Nemesis
  • Re: Virtex 4 DCM problem, Martin Thompson
    • Re: Virtex 4 DCM problem, Nemesis
      • Re: Virtex 4 DCM problem, Nemesis
      • Re: Virtex 4 DCM problem, Martin Thompson
      • Re: Virtex 4 DCM problem, Nemesis
      • Re: Virtex 4 DCM problem, adi
• Help Need about reconfiguring the PLL with prescale counter n and multiply counter m, ajin1983
• asic gate count, vijayant.rutgers@xxxxxxxxx
  • Re: asic gate count, Mike Treseler
  • Re: asic gate count, ghelbig
    • Re: asic gate count, Muzaffer Kal
• Inconsistent File Reading/writing in binary format using MicroBlaze, Bathala
• Snythesis error, Thorsten Kiefer
  • Re: Snythesis error, John_H
    • Re: Snythesis error, Thorsten Kiefer
  • Re: Snythesis error, Kevin Neilson
    • Re: Snythesis error, Thorsten Kiefer
      • Re: Snythesis error, Mike Treseler
      • Re: Snythesis error, Thomas Stanka
      • Re: Snythesis error, Mike Treseler
      • Re: Snythesis error, Andy
  • Re: Snythesis error, Andy Peters
    • Re: Snythesis error, Thorsten Kiefer
• Pre and Post Synthesis Simulation mismatch, robquigley
  • Re: Pre and Post Synthesis Simulation mismatch, John_H
  • Re: Pre and Post Synthesis Simulation mismatch, Muzaffer Kal
• Simulation tools for Xilinx ISE, Michael
  • Re: Simulation tools for Xilinx ISE, ghelbig
    • Re: Simulation tools for Xilinx ISE, Michael
  • Re: Simulation tools for Xilinx ISE, Kevin Neilson
    • Message not available
      • Re: Simulation tools for Xilinx ISE, Michael
      • Re: Simulation tools for Xilinx ISE, Kevin Neilson
      • Re: Simulation tools for Xilinx ISE, Michael
      • Re: Simulation tools for Xilinx ISE, Kevin Neilson
      • Re: Simulation tools for Xilinx ISE, Chumnarn P.
      • Re: Simulation tools for Xilinx ISE, Michael
      • Re: Simulation tools for Xilinx ISE, HT-Lab
      • Re: Simulation tools for Xilinx ISE, lm317t
      • Re: Simulation tools for Xilinx ISE, Nico Coesel
• Xilinx JTAG Linux programming, Habib Bouaziz-Viallet
• "Multi-source in Unit" Verilog synthesis woes, NRClark
  • Re: "Multi-source in Unit" Verilog synthesis woes, Alvin Andries
    • Re: "Multi-source in Unit" Verilog synthesis woes, Gabor
• DOS script file to synthesize a VHDL design, Sue
  • Re: DOS script file to synthesize a VHDL design, HT-Lab
  • Re: DOS script file to synthesize a VHDL design, Brian Drummond
    • Re: DOS script file to synthesize a VHDL design, Alain
• Actel Cortex, John Aderseen
  • Re: Actel Cortex, job
• Which to learn: Verilog vs. VHDL?, Michael
  • Re: Which to learn: Verilog vs. VHDL?, Mike Treseler
  • Re: Which to learn: Verilog vs. VHDL?, RCIngham
    • Re: Which to learn: Verilog vs. VHDL?, Jim Lewis
  • Re: Which to learn: Verilog vs. VHDL?, Kevin Neilson
    • Re: Which to learn: Verilog vs. VHDL?, Eric Smith
  • Re: Which to learn: Verilog vs. VHDL?, Fei Liu
    • Re: Which to learn: Verilog vs. VHDL?, Brian Drummond
  • Re: Which to learn: Verilog vs. VHDL?, lm317t
    • Re: Which to learn: Verilog vs. VHDL?, Eric Smith
      • Re: Which to learn: Verilog vs. VHDL?, lm317t
  • Re: Which to learn: Verilog vs. VHDL?, Jim Lewis
• Chipscope 9.2 in XPS, kislo
• XST support for User Defined Primitives, Goli
  • Re: XST support for User Defined Primitives, Brian Drummond
  • Re: XST support for User Defined Primitives, mk
• HiTech Global Eval boards?, pdudley1@xxxxxxxxxxx
  • Re: HiTech Global Eval boards?, morphiend
• Question about Spartan 3E starter kit, Michael
  • Re: Question about Spartan 3E starter kit, Symon
    • Re: Question about Spartan 3E starter kit, Michael
• become crorepati in less than one year by trading into indian stock market optiontrading., optionmaster
• Spartan3E startup problems, kislo
  • Re: Spartan3E startup problems, kislo
    • Re: Spartan3E startup problems, sky465nm
      • Re: Spartan3E startup problems, kislo
      • Re: Spartan3E startup problems, kislo
      • Re: Spartan3E startup problems, Moazzam
• simple example with timing problems, Thorsten Kiefer
  • Re: simple example with timing problems, Thorsten Kiefer
    • Re: simple example with timing problems, KJ
      • Re: simple example with timing problems, Thorsten Kiefer
• CF (systemace) SD card, etc performance, Antti
  • Re: CF (systemace) SD card, etc performance, Antti
• Need help on UNISIM.Vcomponents.all, LC
  • Re: Need help on UNISIM.Vcomponents.all, Arlet Ottens
    • Re: Need help on UNISIM.Vcomponents.all, LC
  • Re: Need help on UNISIM.Vcomponents.all, vladitx
    • Re: Need help on UNISIM.Vcomponents.all, LC
• high noise/signal in a simple serial to mono dac module, Fei Liu
  • Re: high noise/signal in a simple serial to mono dac module, kevin93
    • Re: high noise/signal in a simple serial to mono dac module, Fei Liu
    • Re: high noise/signal in a simple serial to mono dac module, Alan Nishioka
      • Re: high noise/signal in a simple serial to mono dac module, Fei Liu
      • Re: high noise/signal in a simple serial to mono dac module, John_H
  • Re: high noise/signal in a simple serial to mono dac module, Fei Liu
• Virtex4 FX PPC and Fsl, u_stadler@xxxxxxxx
  • Re: Virtex4 FX PPC and Fsl, damak . taheni
• ISE 9.2 and Windriver, Thorsten Kiefer
  • Re: ISE 9.2 and Windriver, Michael Trim
• 64 bit WebPack, Roger
  • Re: 64 bit WebPack, Eric Smith
    • Re: 64 bit WebPack, David Brown
      • Re: 64 bit WebPack, Eric Smith
      • Message not available
      • Re: 64 bit WebPack, David Brown
  • Re: 64 bit WebPack, Roger
    • Re: 64 bit WebPack, Gavin Scott
    • Re: 64 bit WebPack, Eric Smith
      • Re: 64 bit WebPack, Roger
• Xilinx tech Xclusive, Lars
  • Re: Xilinx tech Xclusive, Symon
    • Re: Xilinx tech Xclusive, Lars
      • Re: Xilinx tech Xclusive, Lars
      • Re: Xilinx tech Xclusive, Marlboro
      • Re: Xilinx tech Xclusive, austin
      • Re: Xilinx tech Xclusive, AugustoEinsfeldt
      • Re: Xilinx tech Xclusive, Jim Granville
      • Re: Xilinx tech Xclusive, Peter Alfke
      • Message not available
      • Re: Xilinx tech Xclusive, Jim Granville
      • Message not available
      • Re: Xilinx tech Xclusive, Eric Smith
• Split register in smaller segments, Michael Meeuwisse
  • Re: Split register in smaller segments, Jonathan Bromley
    • Re: Split register in smaller segments, Michael Meeuwisse
      • Re: Split register in smaller segments, Jonathan Bromley
      • Re: Split register in smaller segments, Michael Meeuwisse
      • Re: Split register in smaller segments, Jonathan Bromley
• Xilinx ISE synthesis error (error:3524 Unexpected end of line.), giorgos . puiklis
• why to trigger a NMI error after just receiving 35 pakcets?, water9580@xxxxxxxxx
  • Re: why to trigger a NMI error after just receiving 35 pakcets?, RCIngham
• You M.ust know this to get Financial Aid!, DownloadTVepisodesejda
• clock instanciation, Thorsten Kiefer
  • Re: clock instanciation, Symon
    • Re: clock instanciation, Thorsten Kiefer
      • Re: clock instanciation, Mike Treseler
      • Re: clock instanciation, Symon
• Specifying strict setup constraint in ISE, Wojciech Zabolotny
  • Re: Specifying strict setup constraint in ISE, Peter Alfke
  • Re: Specifying strict setup constraint in ISE, John_H
    • Re: Specifying strict setup constraint in ISE, Gabor
    • Re: Specifying strict setup constraint in ISE, Symon
• Xilinx FFT C-sim model, Pete
  • Re: Xilinx FFT C-sim model, Marty Ryba
  • Re: Xilinx FFT C-sim model, Patrick Dubois
• Re: Serial Transmission w/o 8B/10B encoding, shakith . fernando
  • Re: Serial Transmission w/o 8B/10B encoding, glen herrmannsfeldt
  • Re: Serial Transmission w/o 8B/10B encoding, Peter Alfke
    • Re: Serial Transmission w/o 8B/10B encoding, shakith . fernando
      • Re: Serial Transmission w/o 8B/10B encoding, Peter Alfke
      • Re: Serial Transmission w/o 8B/10B encoding, Peter Alfke
      • Re: Serial Transmission w/o 8B/10B encoding, Eric Smith
      • Re: Serial Transmission w/o 8B/10B encoding, glen herrmannsfeldt
      • Re: Serial Transmission w/o 8B/10B encoding, Brian Drummond
• Xilinx CPLD programming tool under Linux, Habib Bouaziz-Viallet
  • Re: Xilinx CPLD programming tool under Linux, DJ Delorie
    • Re: Xilinx CPLD programming tool under Linux, Habib Bouaziz-Viallet
      • Re: Xilinx CPLD programming tool under Linux, Uwe Bonnes
      • Re: Xilinx CPLD programming tool under Linux, Habib Bouaziz-Viallet
      • Re: Xilinx CPLD programming tool under Linux, Uwe Bonnes
      • Re: Xilinx CPLD programming tool under Linux, Habib Bouaziz-Viallet
      • Re: Xilinx CPLD programming tool under Linux, Eric Smith
• looking for critique for a spartan3a lcd controller verilog module, Fei Liu
  • Re: looking for critique for a spartan3a lcd controller verilog module, Fei Liu
• Disable optimisation - Ring oscillator, Franck Y
  • Re: Disable optimisation - Ring oscillator, Uwe Bonnes
    • Re: Disable optimisation - Ring oscillator, Franck Y
      • Re: Disable optimisation - Ring oscillator, Uwe Bonnes
  • Re: Disable optimisation - Ring oscillator, Jim Granville
    • Re: Disable optimisation - Ring oscillator, Franck Y
    • Re: Disable optimisation - Ring oscillator, radarman
  • Re: Disable optimisation - Ring oscillator, Kolja Sulimma
• 32 bit multiplier, VIPS
  • Re: 32 bit multiplier, Alvin Andries
    • Re: 32 bit multiplier, Tim (one of many)
      • Re: 32 bit multiplier, Symon
      • Re: 32 bit multiplier, Ray Andraka
      • Re: 32 bit multiplier, Uwe Bonnes
      • Re: 32 bit multiplier, Peter Alfke
      • Re: 32 bit multiplier, Kolja Sulimma
      • Re: 32 bit multiplier, Jim Granville
  • Re: 32 bit multiplier, Jim Granville
• Starting a PCI Express Application, jjlindula@xxxxxxxxxxx
  • Re: Starting a PCI Express Application, sky465nm
  • Re: Starting a PCI Express Application, Bernard Esteban
• Intel plans to tackle cosmic ray threat, Symon
  • Re: Intel plans to tackle cosmic ray threat (actually they have been working on it for at least five years...austin), austin
    • Re: Intel plans to tackle cosmic ray threat (actually they have been working on it for at least five years...austin), Symon
      • Re: Intel plans to tackle cosmic ray threat (actually they have been working on it for at least five years...austin), austin
      • Re: Intel plans to tackle cosmic ray threat (actually they have been working on it for at least five years...austin), austin
      • Re: Intel plans to tackle cosmic ray threat (actually they have been working on it for at least five years...austin), Colin Paul Gloster
      • Re: Intel plans to tackle cosmic ray threat (actually they have been working on it for at least five years...austin), austin
      • Re: Intel plans to tackle cosmic ray threat (actually they have been working on it for at least five years...austin), Colin Paul Gloster
      • Re: Intel plans to tackle cosmic ray threat (actually they have been working on it for at least five years...austin), Jon Elson
    • Re: Intel plans to tackle cosmic ray threat (actually they have been working on it for at least five years...austin), austin
      • Re: Intel plans to tackle cosmic ray threat (actually they have been working on it for at least five years...austin), Symon
      • Re: Intel plans to tackle cosmic ray threat (actually they have been working on it for at least five years...austin), austin
      • Re: Intel plans to tackle cosmic ray threat (actually they have been working on it for at least five years...austin), Symon
      • Re: Intel plans to tackle cosmic ray threat (actually they have been working on it for at least five years...austin), Jon Elson
      • Re: Intel plans to tackle cosmic ray threat (actually they have been working on it for at least five years...austin), austin
      • Re: Intel plans to tackle cosmic ray threat (actually they have been working on it for at least five years...austin), cs_posting
      • Re: Intel plans to tackle cosmic ray threat (actually they have been working on it for at least five years...austin), Symon
      • Re: Intel plans to tackle cosmic ray threat (actually they have been working on it for at least five years...austin), Marty Ryba
      • Re: Intel plans to tackle cosmic ray threat (actually they have beenworking on it for at least five years...austin), Jim Granville
      • Re: Intel plans to tackle cosmic ray threat (actually they have been working on it for at least five years...austin), Jon Elson
      • Re: Intel plans to tackle cosmic ray threat (actually they have been working on it for at least five years...austin), Colin Paul Gloster
      • Re: Intel plans to tackle cosmic ray threat (actually they have been working on it for at least five years...austin), austin
    • Re: Intel plans to tackle cosmic ray threat (actually they have been working on it for at least five years...austin), Colin Paul Gloster
      • Space - Xilinx Frontier?, austin
  • Re: Intel plans to tackle cosmic ray threat, austin
• NoisII or else., LC
  • Re: NoisII or else., Górski Adam
    • Re: NoisII or else., LC
      • Re: NoisII or else., Górski Adam
      • Re: NoisII or else., LC
    • Re: NoisII or else., David Spencer
      • Re: NoisII or else., LC
      • Re: NoisII or else., Górski Adam
      • Re: NoisII or else., LC
• OBUF gate delay, jamicrotech
  • Re: OBUF gate delay, Symon
    • Re: OBUF gate delay, Symon
  • Re: OBUF gate delay, John_H
• MIG/Corgen to XPS core insertion, xenix
  • Re: MIG/Corgen to XPS core insertion, xenix
    • Re: MIG/Corgen to XPS core insertion, xenix
      • Re: MIG/Corgen to XPS core insertion, xenix
• Avalon Bus <-> Wishbone Bus, benn
  • Re: Avalon Bus <-> Wishbone Bus, KJ
  • Re: Avalon Bus <-> Wishbone Bus, Mark McDougall
  • Re: Avalon Bus <-> Wishbone Bus, ghelbig
• Modify POF with new ESB (ROM) content?, radarman
  • Re: Modify POF with new ESB (ROM) content?, Antti
    • Re: Modify POF with new ESB (ROM) content?, Petter Gustad
      • Re: Modify POF with new ESB (ROM) content?, Antti
      • Re: Modify POF with new ESB (ROM) content?, Petter Gustad
      • Re: Modify POF with new ESB (ROM) content?, Antti
      • Re: Modify POF with new ESB (ROM) content?, Petter Gustad
      • Re: Modify POF with new ESB (ROM) content?, Antti
      • Re: Modify POF with new ESB (ROM) content?, Petter Gustad
      • Re: Modify POF with new ESB (ROM) content?, Antti
      • Re: Modify POF with new ESB (ROM) content?, Petter Gustad
      • Re: Modify POF with new ESB (ROM) content?, cs_posting
      • Re: Modify POF with new ESB (ROM) content?, Jim Granville
      • Re: Modify POF with new ESB (ROM) content?, Uwe Bonnes
      • Re: Modify POF with new ESB (ROM) content?, Andreas Ehliar
      • Re: Modify POF with new ESB (ROM) content?, Petter Gustad
      • Re: Modify POF with new ESB (ROM) content?, Brian Drummond
• FPGA configuration mode on ML310, grant0920
  • Re: FPGA configuration mode on ML310, Antti
    • Re: FPGA configuration mode on ML310, grant0920
  • Re: FPGA configuration mode on ML310, Ed McGettigan
    • Re: FPGA configuration mode on ML310, grant0920
• 19th IEEE/IFIP Rapid System Prototyping Symposium, shing
• Xilinx xilfatfs and systemACE speed issue, Antti
  • Re: Xilinx xilfatfs and systemACE speed issue, morphiend
    • Re: Xilinx xilfatfs and systemACE speed issue, Antti
    • Re: Xilinx xilfatfs and systemACE speed issue, Antti
• Use of floating point numbers in xilinx EDK ........., nivesh
  • Re: Use of floating point numbers in xilinx EDK ........., Andy
• problem with synthesis of a state machine, Fei Liu
  • Re: problem with synthesis of a state machine, Fei Liu
  • Re: problem with synthesis of a state machine, glen herrmannsfeldt
  • Re: problem with synthesis of a state machine, Muzaffer Kal
    • Re: problem with synthesis of a state machine, Fei Liu
      • Re: problem with synthesis of a state machine, Muzaffer Kal
• Re: A Challenge for serialized processor design and implementation, Jim Granville
• Re: Virtex-5 FXT coming soon?, Simon
  • Re: Virtex-5 FXT coming soon?, Peter Alfke
    • Re: Virtex-5 FXT coming soon?, Simon
      • Re: Virtex-5 FXT coming soon?, Ed McGettigan
• PLA datasheet - PLS161, Joseph
  • Re: PLA datasheet - PLS161, Jim Granville
    • Re: PLA datasheet - PLS161, Jim Granville
• Project Ideas, Ankit
  • Re: Project Ideas, Frank Buss
• Xilinx inferred FIFOs, Brad Smallridge
  • Re: Xilinx inferred FIFOs, austin
    • Re: Xilinx inferred FIFOs, Brad Smallridge
      • Re: Xilinx inferred FIFOs, austin
      • Re: Xilinx inferred FIFOs, Frank Buss
      • Re: Xilinx inferred FIFOs, Jim Granville
      • Re: Xilinx inferred FIFOs, Peter Alfke
      • Re: Xilinx inferred FIFOs, Frank Buss
      • Re: Xilinx inferred FIFOs, Eric Smith
      • Re: Xilinx inferred FIFOs, Kevin Neilson
• UK Embedded Masterclass, richard
  • <Possible follow-ups>
  • UK Embedded Masterclass, richard
• Examples for Spartan3 StarterKit, Thorsten Kiefer
  • Re: Examples for Spartan3 StarterKit, Jaime Andres Aranguren Cardona
• Xilinx FPGA + SMPS, sky465nm
  • Re: Xilinx FPGA + SMPS, Symon
    • Re: Xilinx FPGA + SMPS, MM
  • Re: Xilinx FPGA + SMPS, austin
    • Re: Xilinx FPGA + SMPS, Nico Coesel
      • Re: Xilinx FPGA + SMPS, Jim Granville
      • Re: Xilinx FPGA + SMPS, Allan Herriman
      • Re: Xilinx FPGA + SMPS, austin
      • Re: Xilinx FPGA + SMPS, austin
• One more question. WebPACK key with ISE, zlyh
  • Re: One more question. WebPACK key with ISE, Andy Peters
• loop back on a MARVELL switch, archana
• Downloading some data from flash memory thru JTAG., climber . tim
• problem with synthesis, Fei Liu
  • Re: problem with synthesis, Muzaffer Kal
• synplify pro generates negative slack, ni
  • Re: synplify pro generates negative slack, Ben Jones
    • Re: synplify pro generates negative slack, ni
      • Re: synplify pro generates negative slack, Kevin Neilson
      • Re: synplify pro generates negative slack, Mike Treseler
      • Re: synplify pro generates negative slack, ni
      • Re: synplify pro generates negative slack, Mike Treseler
• Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1), mdschulte
  • Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1), Symon
  • Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1), David Brown
    • Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1), dalai lamah
      • Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1), David Brown
      • Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1), Symon
      • Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1), David Brown
      • Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1), dalai lamah
• No synchronization word in prom file (XILINX)?, Bubba
  • Re: No synchronization word in prom file (XILINX)?, Bubba
    • Re: No synchronization word in prom file (XILINX)?, Bubba
• Re: Power Estimation of Microblaze (Power PC) based architectures, ahosyney
• Spartan3 JTAG flash In System Programming over Ethernet, cpandya
  • Re: Spartan3 JTAG flash In System Programming over Ethernet, Petter Gustad
    • Re: Spartan3 JTAG flash In System Programming over Ethernet, Fei Liu
    • Re: Spartan3 JTAG flash In System Programming over Ethernet, Nico Coesel
      • Re: Spartan3 JTAG flash In System Programming over Ethernet, cs_posting
• Beginner's silly question about ICAP, g . drozdzowski
  • Re: Beginner's silly question about ICAP, austin
  • Re: Beginner's silly question about ICAP, Jens Hagemeyer
    • Re: Beginner's silly question about ICAP, g . drozdzowski
• Protecting design from being downloaded on other (similar) FPGA devices, maverick
  • Re: Protecting design from being downloaded on other (similar) FPGA devices, Antti
    • Re: Protecting design from being downloaded on other (similar) FPGA devices, austin
  • Re: Protecting design from being downloaded on other (similar) FPGA devices, John McCaskill
    • Re: Protecting design from being downloaded on other (similar) FPGA devices, MM
      • Re: Protecting design from being downloaded on other (similar) FPGA devices, maverick
      • Re: Protecting design from being downloaded on other (similar) FPGA devices, Antti
      • Re: Protecting design from being downloaded on other (similar) FPGA devices, Antti
      • Re: Protecting design from being downloaded on other (similar) FPGA devices, Krzysztof Kepa
      • Re: Protecting design from being downloaded on other (similar) FPGA devices, Alan Nishioka
      • Re: Protecting design from being downloaded on other (similar) FPGA devices, MM
  • Re: Protecting design from being downloaded on other (similar) FPGA devices, Bob Smith
    • Re: Protecting design from being downloaded on other (similar) FPGA devices, Antti
      • Re: Protecting design from being downloaded on other (similar) FPGA devices, Andreas Ehliar
• EDK 10.1 first impressions, Antti
  • Re: EDK 10.1 first impressions, Antti
    • Re: EDK 10.1 first impressions, Patrick Dubois
  • Re: EDK 10.1 first impressions, Andy Peters
    • Re: EDK 10.1 first impressions, Antti
    • Re: EDK 10.1 first impressions, Ed McGettigan
      • Re: EDK 10.1 first impressions, Kolja Sulimma
• Re: async clk input, clock glitches, Jon Elson
  • <Possible follow-ups>
  • Re: async clk input, clock glitches, Jon Elson
    • Re: async clk input, clock glitches, Peter Alfke
      • Re: async clk input, clock glitches, Peter Alfke
      • Re: async clk input, clock glitches, Torsten Landschoff
      • Re: async clk input, clock glitches, Nial Stewart
      • Re: async clk input, clock glitches, Symon
      • Re: async clk input, clock glitches, Muzaffer Kal
• Conterfeit parts guidance, craig . taylor
  • Re: Conterfeit parts guidance, Morten Leikvoll
    • Re: Conterfeit parts guidance, Symon
    • Re: Conterfeit parts guidance, jon
  • Re: Conterfeit parts guidance, Nico Coesel
    • Re: Conterfeit parts guidance, Jim Granville
      • Re: Conterfeit parts guidance, pdorsey
      • Re: Conterfeit parts guidance, Jim Granville
      • Re: Conterfeit parts guidance, Craig
  • Re: Conterfeit parts guidance, sky465nm
• Re: counterfeit Xilinx ?, craig . taylor
  • Re: counterfeit Xilinx ?, Jim Granville
    • Re: counterfeit Xilinx ?, Peter Alfke
      • Re: counterfeit Xilinx ?, Jim Granville
      • Re: counterfeit Xilinx ?, Craig
      • Re: counterfeit Xilinx ?, Jon Elson
  • <Possible follow-ups>
  • Re: counterfeit Xilinx ?, John McCaskill
    • Re: counterfeit Xilinx ?, Jon Elson
      • Re: counterfeit Xilinx ?, John_H
      • Re: counterfeit Xilinx ?, Jon Elson
      • Re: counterfeit Xilinx ?, Uwe Bonnes
      • Re: counterfeit Xilinx ?, Jim Granville
      • Re: counterfeit Xilinx ?, Jon Elson
      • Re: counterfeit Xilinx ?, Jim Granville
  • Re: counterfeit Xilinx ?, -jg
• ModelSim XE problems with a VHDL coregen in a Virtex 5, Dan K
  • Re: ModelSim XE problems with a VHDL coregen in a Virtex 5, Sean Durkin
• Xilinx ISE 10.1 Ubuntu Linux Installation - Driver Installation Problem, disq
  • Re: Xilinx ISE 10.1 Ubuntu Linux Installation - Driver Installation ?Problem, Uwe Bonnes
• Xst_Choice nodes, robquigley
  • Re: Xst_Choice nodes, Kolja Sulimma
• "Number of BSCANs: 2 out of 1 200%", Pablo
  • Re: "Number of BSCANs: 2 out of 1 200%", tarmopalm
    • Re: "Number of BSCANs: 2 out of 1 200%", Zara
  • Re: "Number of BSCANs: 2 out of 1 200%", Torsten Landschoff
    • Re: "Number of BSCANs: 2 out of 1 200%", Pablo
      • Re: "Number of BSCANs: 2 out of 1 200%", Moazzam
      • Re: "Number of BSCANs: 2 out of 1 200%", Pablo
• coregenerator bram in synplify pro error, ni
  • Re: coregenerator bram in synplify pro error, Duane Clark
    • Re: coregenerator bram in synplify pro error, ni
      • Re: coregenerator bram in synplify pro error, Duane Clark
      • Re: coregenerator bram in synplify pro error, ni
    • Re: coregenerator bram in synplify pro error, Brian Drummond
      • Re: coregenerator bram in synplify pro error, Jeff Cunningham
      • Re: coregenerator bram in synplify pro error, Duane Clark
      • Re: coregenerator bram in synplify pro error, Mike Treseler
      • Message not available
      • Re: coregenerator bram in synplify pro error, Duane Clark
• Re: ISE 10.0 finally with multi-threading and SV support ?, Andy Peters
• Why does ISE 9.2 optimize out the logic, fl
• now I can talk about it..., austin
  • Re: now I can talk about it..., Jon Beniston
    • Re: now I can talk about it..., austin
      • Re: now I can talk about it..., austin
      • Re: now I can talk about it..., Frank Buss
      • Re: now I can talk about it..., Jim Granville
    • Re: now I can talk about it..., Peter Alfke
      • Re: now I can talk about it..., Jon Beniston
      • Re: now I can talk about it..., Peter Alfke
      • Re: now I can talk about it..., austin
    • Re: now I can talk about it..., austin
  • Re: now I can talk about it..., paragon . john
    • Re: now I can talk about it..., Symon
      • Re: now I can talk about it..., paragon . john
  • Re: now I can talk about it..., sky465nm
• ISE 9.2i project question, robquigley
  • Re: ISE 9.2i project question, robquigley
• Antii, can you give us an update?, Nial Stewart
  • Re: Antii, can you give us an update?, Peter Alfke
    • Re: Antii, can you give us an update?, Antti
    • Re: Antii, can you give us an update?, KJ
      • Re: Antii, can you give us an update?, Antti
  • Re: Antii, can you give us an update?, Antti
    • Re: Antii, can you give us an update?, Antti
      • Re: Antii, can you give us an update?, Brian Drummond
      • Re: Antii, can you give us an update?, Antti
      • Re: Antii, can you give us an update?, Antti
      • Re: Antii, can you give us an update?, Brian Drummond
• Re: JTAG: First of 4 Spartan-3E always UNKNOWN, Andrew Greensted
  • Re: JTAG: First of 4 Spartan-3E always UNKNOWN, Andrew Greensted
    • Re: JTAG: First of 4 Spartan-3E always UNKNOWN, Nico Coesel
      • Re: JTAG: First of 4 Spartan-3E always UNKNOWN, Andrew Greensted
  • <Possible follow-ups>
  • Re: JTAG: First of 4 Spartan-3E always UNKNOWN, sky465nm
    • Re: JTAG: First of 4 Spartan-3E always UNKNOWN, Antti
      • Re: JTAG: First of 4 Spartan-3E always UNKNOWN, sky465nm
  • Re: JTAG: First of 4 Spartan-3E always UNKNOWN, colin
  • Re: JTAG: First of 4 Spartan-3E always UNKNOWN, job
• Re: increase memory of microblaze, ales . gorkic
• Simple (?) timing constraint for output pins, Torsten Landschoff
  • Re: Simple (?) timing constraint for output pins, job
    • Re: Simple (?) timing constraint for output pins, Torsten Landschoff
      • Re: Simple (?) timing constraint for output pins, MM
      • Re: Simple (?) timing constraint for output pins, Torsten Landschoff
      • Re: Simple (?) timing constraint for output pins, Torsten Landschoff
  • Re: Simple (?) timing constraint for output pins, Torsten Landschoff
• Re: Webpack 10.1 on 64-bit linux, jonas
  • Re: Webpack 10.1 on 64-bit linux, pillar2012@xxxxxxxxx
• Re: PCI Express Configuration Testing, water9580@xxxxxxxxx
  • Re: PCI Express Configuration Testing, Rube Bumpkin
• Re: Xilinx and Modelsim?, ghelbig
  • Re: Xilinx and Modelsim?, Jeff Cunningham
    • Re: Xilinx and Modelsim?, Brian Drummond
  • <Possible follow-ups>
  • Re: Xilinx and Modelsim?, waing gyi
    • Re: Xilinx and Modelsim?, Chumnarn P.
• Re: ISE 10.1 - Initial experience, emeb
  • Re: ISE 10.1 - Initial experience, Kolja Sulimma
    • Re: ISE 10.1 - Initial experience, Jim Granville
      • Re: ISE 10.1 - Initial experience, Kolja Sulimma
    • Re: ISE 10.1 - Initial experience, emeb
  • <Possible follow-ups>
  • Re: ISE 10.1 - Initial experience, Sonal Santan
  • Re: ISE 10.1 - Initial experience, Andy Peters
    • Re: ISE 10.1 - Initial experience, Phil Hays
      • Re: ISE 10.1 - Initial experience, Phil Hays
      • Re: ISE 10.1 - Initial experience, Andy Peters
• Re: Using USB programming cables from Xilinx and Lattice on one Windows machine, Sean Durkin
  • Re: Using USB programming cables from Xilinx and Lattice on one Windows machine, sky465nm
  • Re: Using USB programming cables from Xilinx and Lattice on one Windows machine, Brian Davis
• Re: Impact won't program XC3S200, does program XC3SD1800A, rponsard@xxxxxxxxx

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newsgroups.derkeiler.com  > Archive  > Comp  > comp.arch.fpga  > 2008-04