Re: Functional Simulation of Virtex-4 Block Memory


When I started with ROMs circa ISE 6.2 the COE thing
wasn't working past some small number of values.
Someone prompty directed me to infer the ROM and not
use the core generator at all.

The VHDL looks something like this:

type i2c_array_type is array(natural range <>) of natural;
constant i2c_data_array : i2c_array_type :=(
0,0,0 -- put your constants here
);
signal i2c_bit_index0 : unsigned(2 downto 0);
begin
i2c_data1 <= i2c_data_array(i2c_dat_index0);

You can use natural,integer,enumerated data,std_logic_vectors,
or records to fit your design data type. All the simulation
data will be visible and the ISE reports will tell you how
many BRAMs were used. I don't think any deeper level of
simulation will provide you more confidence.

If you post your code, I'm sure we can help you debug some
of the issues regarding conversions and the like.

Brad Smallridge
AiVision




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