Re: Problem writing quadrature decoder

Peter Alfke wrote:

Well, this is a challenge.

I am working on a design that uses 4 LUTs and 4 flip-flops,
takes in raw A and B inputs plus a clock
and outputs synchronously decoded CE and U/D signals to control a
binary counter.
There are 3 configuration options: 1, 2, or 4 counts per 360 degree
contact cycle.
And bounce is suppressed, and kept away from the counter :-)

"Everything you always wanted to have in a quadrature detector'"

Hmmm,
Can you explain how bounce can be suppressed in a 4 count design ?
There, you cannot distinguish between a change in direction, and
a contact bounce, as they have the same signature ?.

Does it also catch false/illegal states in the 4 count mode ?

I have heard of very high apparent edge rates in mechanical systems,
caused by shock propogations (certainly enough to stress a Software
Solution) - so a 50MHz+ clock is not as silly as it may sound :)

- Jim Granville,

.

Relevant Pages

  • Re: Any ideas on how to do this?
    ... I have to describe and design a 32 bit binary to 40 bits BCD converter. ... of the number you loaded into the binary counter. ... 10MHz clock, it'll only take about 429 seconds. ...
    (sci.electronics.design)
  • Re: ISE software bug???
    ... The design & report files attached below. ... TIMING REPORT ... Add Generic Clock Buffer: 8 ...
    (comp.arch.fpga)
  • Re: Coding style, wait statement, sensitivity list and synthesis.
    ... >> a double-edge sensitive register. ... >> which also allowed some pretty exotic scan/functional clock designs. ... >> this coding style: ... > In a design review, I require all multiple clock and clock ...
    (comp.lang.vhdl)
  • Re: Modulo-10 counter
    ... and would affect your design if you would play ... multipliers in your datapath without being bothered by clock skew ... The obvious thing to consider is the routing delay. ...
    (comp.arch.fpga)
  • Re: regarding the post PnR timing simulation.....
    ... Regarding the timing violation. ... quality of the clock is essential, for instance jitter, duty cycle, phase ... This is all what I can guess without knowing your design. ...
    (comp.arch.fpga)