Re: async clk input, clock glitches

KJ wrote:

"Jim Granville" <no.spam@xxxxxxxxxxxxxxxxxxxxxx> wrote in message news:47eebe69@xxxxxxxxxxxxxxx

KJ wrote:

Your post never mentioned anything about having measured a slow edge on the 4MHz signal either. If the edge rate is within spec, adding a Schmitt trigger will have no effect.

Not entirely true.
In the real analog world, there are other details that can
trip you up. Ground level shifting and series inductances all
conspire against clean digital operation...

(The best schmitt is a non-inverting one.)



The usefulness of the trigger from an engineering perspective is to turn a slow edge into a faster one in order to meet input characteristics of a part that can not tolerate the slower edge.

Yes, but it does more as well. The output of a schmitt now references
against the local ground, and so you have increased the tolerance of
inter-system ground bounce.

Use of a schmitt trigger to address any of the issues that you mention would only be considered if there are some other physical constraints that precludes the proper engineering solution which would consist of
- Termination
- Proper grounding
- Differential signalling

for the simple reason that the trigger would not be addressing the root cause issues that you brought up.

Of course, but we work in the real world and if (eg) the design
has to work across multiple PCBs, then the 'proper grounding'
may not be on the table.
Differential signaling is great, but you may be forced to deploy to
a i2c or SPI interface standard - or just be told that many wires
are too expensive!,

Schmitts also allow designers to deploy EMC measures, often late
in the design flow.

Pin Configurable schmitts are common in CPLDs, and I know one vendor
who put them there, because we provided examples of when/how they
were needed in real world applications.

-jg




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