Re: async clk input, clock glitches


"Antti" <Antti.Lukats@xxxxxxxxxxxxxx> wrote in message
news:ff1c62b5-f856-4740-9c12-5e303525500b@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
On 30 Mrz., 22:42, j...@xxxxxxxxxxx wrote:
On Mar 29, 9:59 pm, Antti <Antti.Luk...@xxxxxxxxxxxxxx> wrote:

that can only happen if the pulse was not latched proper level for
many clocks of 50mhz, something i can really not understand.

well all those errors have disappeared happily, without schmit trigger
or any other magic


Just what was the change anyway? Getting rid of using the strobe to clock
things or something else?

KJ


.

Relevant Pages

  • Re: Antii, can you give us an update?
    ... When a high-frequency clocks a flip-flop that has a significantly ... But there can be additional transitions ... But NEVER a missing transition on Q. ... Keep in mind that Antti never actually measured a missing strobe, ...
    (comp.arch.fpga)
  • Re: Antii, can you give us an update?
    ... When a high-frequency clocks a flip-flop that has a significantly ... But NEVER a missing transition on Q. ... Keep in mind that Antti never actually measured a missing strobe, ... extra clocks NEVER ...
    (comp.arch.fpga)
  • Re: async clk input, clock glitches
    ... many clocks of 50mhz, something i can really not understand. ... Getting rid of using the strobe to clock ... there was measurable error rate for both extra and missing strobes. ... where I had to filter the signals, so at design change i removed some ...
    (comp.arch.fpga)
  • Re: Number of GCLKs: 9 out of 8 112% (OVERMAPPED)
    ... I'd suggest getting rid of at least one clock. ... Notice which clocks are assigned to GCLKs. ... Probably just a matter of semantics, but gated clocks shoud be avoided like the plague for synchronous designs. ...
    (comp.arch.fpga)
  • Re: The Flip Clock
    ... I own a lot of very old electric and wind up clocks and an old coocoo ... clock.My wall clock on my living room wall is an antique Ansonia octogon ... can't get rid of them. ...
    (rec.radio.shortwave)