Re: async clk input, clock glitches

Antti wrote:
<paste>
if any FF is clocked by local routing in Actel FPGA then it is
complete disaster

So the 'key' trigger condition is using local routing for clock ?

Hi all

the FPGA resource % wasnt the thing after further reducing the
utilization down to 37% the error rate increased and missing pulses re-
apperared!

No, but these tests are to see if there is a CHANGE in failure rate,
as any change indicates a 'cross-talk sensistivity' - and you
do see significant changes in error rates :)

but, when then removing the flop from 4mhz strobe AND changing
synplify constraints:

What did changing the constraints do ?


45 minutes up and running no error detected so far
pulse count >10G

sure I need the design to work without error with FPGA utilization

=90% but seeing the PCB to not fail on the strobe is already some
indicator that there is really nothing wrong with the 4mhz strobe
signal, so no external conditioning required

Do you know if this is a time-domain problem (Tsu/Th) or a
crosstalk problem ? (device fabric not good enough for clocks)
or models not matching loading/skew effects in real device
(and being not as well tested, has been mised by Actel?)

Did someone else find this issue with local clocks == dodgy - ISTR an earlier thread ?

-jg

.