Re: async clk input, clock glitches


"Antti" <Antti.Lukats@xxxxxxxxxxxxxx> wrote in message
news:368339ad-6636-4a63-a57e-9785bc3ac581@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
On 30 Mrz., 21:42, Jim Granville <no.s...@xxxxxxxxxxxxxxxxxxxxxx>

http://www.actel.com/documents/Clock_Skew_AN.pdf

look as example figure 9 there how do you like if your FPGA vendor
suggest using this type of clock distribution?

i do not have any local clocks, not any more, but i have seen those
effects very well.

So now everything is clocked by the 50 MHz clock then? Nothing by the 4 MHz
strobe (or anything derived from it)?

I assumed the FGPA fitter tools to take care those
situations or issue warning

It would show up when doing static timing analysis under fastest conditions
(i.e. when analyzing for minimum delays, Tco, etc.) and where analysis
between clock domains is enabled.

at least or that it shows in post place
simulation, but no. those Actel FF that clock 100% false can pass
fitter and show no problems in post-place sims also.


Post-place sims do not catch timing errors, they do not catch metastability
problems. Generally they just take a long time to run.

my failure rate change may also be just different fitter run
differences. I have no almost all working, that is no double or
missing strobes, and the 50mhz domain part also working ok

Congrats....now try the freeze spray and the hot air gun to make sure that
you're not sensitive to temperature

KJ


.

Relevant Pages

  • Re: FPGA Journal Article
    ... domains and fine tune the designs timing constraints in those clock ... For reconfigurable computing, as a comodity general purpose processor ... cross clock domains. ... The practial clocking environment for this would be a series of edge ...
    (comp.arch.fpga)
  • Make a signal free for glitches?
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    (comp.arch.fpga)
  • Re: Actel SX-A Timing Constraints Issues
    ... Shouldn't we constrain the inputs/outputs in each clock domain ... domains and allow the tools to put more effort on the 48MHz signals. ... clock domains short of listing all of the different signals in each ...
    (comp.arch.fpga)
  • Re: Dealing wiht multiple clock domain...cleanly?
    ... I'm working on an Xilinx Spartan FPGA design which will consists of the ... I would do this with two separate clock ... I can do this on the FPGA as well. ... -what do FPGA people do when they have to deal with 6-10 clock domains? ...
    (comp.arch.fpga)
  • Re: Mixed clocked/combinatorial coding styles (another thread)
    ... system clock is significantly faster than the interface clock, ... interface clock can be used as a signal instead of a clock. ... is that if they sell fewer chips, they have a smaller budget for the ... What do you mean by "clock domains that are larger than 1 FF in each direction"? ...
    (comp.lang.vhdl)