Re: async clk input, clock glitches


"Jim Granville" <no.spam@xxxxxxxxxxxxxxxxxxxxxx> wrote in message
news:47efdf2b@xxxxxxxxxxxxxxx
Antti wrote:
<paste>
if any FF is clocked by local routing in Actel FPGA then it is
complete disaster

So the 'key' trigger condition is using local routing for clock ?


More likely, it's his use of a flip flop output which goes metastable as a
clock input to another flop.

the FPGA resource % wasnt the thing after further reducing the
utilization down to 37% the error rate increased and missing pulses re-
apperared!

No, but these tests are to see if there is a CHANGE in failure rate,
as any change indicates a 'cross-talk sensistivity' - and you
do see significant changes in error rates :)


New routes produce differences in actual device timing which precludes one
from making any judgments about 'cross-talk sensitivity' based on changes in
failure rates....

Crosstalk happens, but is usually pretty far down on the checklist of actual
causes for design failure....after timing, clock domain crossing (which is
really timing as well), signal quality and power.

KJ


.

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