Re: Synthesisable Timer in VHDL


"move" <liubenyuan@xxxxxxxxx> wrote in message
news:ce01257f-651a-4792-aa92-6238b902e219@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
hi all:

i am currently working on a "toy" design of my first big project (in
VHDL) on the Xilinx Spartan III starter kit. now facing a timer
problem and i could not properlly solve it using my limited design
experience, here is it:

module A will prepare data for output (node : dout(7 downto 0)) to
module B when it receive a READY signal from B. in order to notify B
that the data is ready on the bus , A will ouput a signal DONE , but
the DONE will be '1' after 30 ms A received signal READY and will just
last 10 ms before going low. I wonder is there any standard or elegant
way of implement the timer in VHDL?

PLZ give me some hint!
thank U all in advance ! :)

1. Create constants of type time (or pass in as generics of type time) the
clock period of your clock and the time period for your delays.
2. Based on the value of those constants/generics compute the number of
clocks that you would need to count (i.e. Max_count := Delay_Time /
Clock_Period)
3. Declare an integer signal in the range from 0 to Max_Count -1
4. Create the code for a counter that counts from 0 to Max_Count - 1. When
you get up to Max_Count - 1 your requested time interval has occurred so do
whatever it is you want to do at that time.

Kevin Jennings


.

Relevant Pages

  • Synthesisable Timer in VHDL
    ... i am currently working on a "toy" design of my first big project (in ... VHDL) on the Xilinx Spartan III starter kit. ... now facing a timer ... way of implement the timer in VHDL? ...
    (comp.arch.fpga)
  • Re: Lahman, how ya doing?
    ... One also has to be careful about books with 'UML' or a specific OOPL in the title; they are good at describing how to express your design in the UML or OOPL syntax but they tend to be short on advice about coming up with a good design in the first place. ... The author has made clear in an early chapter that the book is about OOA, and what UML is introduced will serve that purpose. ... When we talked about things like hardware propagation delays before you didn't seem to think they were relevant (i.e., all the controller processing could be completed in a base clock tick interval (100 ms) in the real controller). ... But speaking of maintainability, if it were to be used in a real-time system with Timer reading the system clock rather than incrementing a counter, could it easily accomodate that? ...
    (comp.object)
  • Re: Questions on VHDL
    ... ModelSim should allow you to "compile" your design and simulate it. ... I would recommend using emacs as the editor for VHDL ... physical memory elements, ... As far as I remember all waves are based on signals created by clock, ...
    (comp.lang.vhdl)
  • Re: Questions on VHDL
    ... ModelSim should allow you to "compile" your design and simulate it. ... I would recommend using emacs as the editor for VHDL ... The synchronous circuits are more predictable than their asynchronous ... physical memory elements, ...
    (comp.lang.vhdl)
  • Re: hello friend i facing a probelm to create code for 8 bit microprocessor
    ... loaded into a program memory as part of the VHDL file - It will not ... Design each component in turn ... The control module is the most difficult par tof the microcomputer to ...
    (comp.lang.vhdl)