Re: async clk input, clock glitches

[snip]
strobe(clk) idle high pulses low, write latch on rising edge
and the strobe IS CLEAN no glitch pure signal tested verified...
after applying the changes that made 0 error for 37% full FPGA
to the full desing (82% full) the resulting design, well still has 0
clock error
but the remaining portions of the design are no longer working..
so i need some more work to get the full design working properly
Antti

No, I understand you do not have the clock - just saying that you SHOULD
have the clock. The interface seems, at best, very flakey to me. If the
strobe was clean you would have zero problems. The system should be 'right
by design' and not have work arounds applied to cover up a problem.

similar design WORKS in Xilinx FPGA always no workarounds needed.

the actel version is optimized for actel fabric, what forced the use
of global
clock lines for some none clock nets, and other changes that reduced
the
logic utilization for Actel target architecture.

the interface is not mine, and it is not flakey, it works and it works
reliable
and i can not change it. right now it also work in my FPGA with 82%
percent full
been working over 6 hours continuous testing, 0 errors.

but with 82% full some of the other logic that worked, stopped
working.
so i need keep cleaning up the design and doing more and more
iterations,
when I remove the global buffers from non global signal the design
would
not fit the target device (actel generates 2 logic per many flip
flops), my
current design still has 22 flip flops mapped to 2 logic cells, and 23
flops
mapped to 4 logic cell per flop, so wastin 91 logic cells or 8% of the
total
resources. I can try to run some more rounds of manual logic
optimization,
but this is not really a funny job. but using larger FPGA or FPGA from
other
vendor would increase the BOM cost for at least 1 usd more likely for
2 usd
what is unacceptable for the design, so i need optimize and optimize
and the
fight actel tools and weirdness.

I know very well that: "any digital design works AS DESIGNED" first
attempt
if it is done "correctly". It really does, but sometimes the way to it
isnt so easy.

so, the strobe is clean, 100% verfied, but there are cases where it
appears
to have problems in actel FPGA.

Antti
to Xilinx I would have saved many month of deep troubleshooting, would
Xilinx had required package options for S3AN.. but now it was just
another
design loss for Xilinx. Maybe S4 will re-introduce small packages who
know
but for this project its too late anyway.





.

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